Document
STB23NM50N, STF23NM50N STP23NM50N, STW23NM50N
N-channel 500 V, 0.162 Ω, 17 A TO-220, TO-220FP, TO-247, D²PAK MDmesh™ II Power MOSFET
Features
Order codes
STB23NM50N STF23NM50N STP23NM50N STW23NM50N
VDSS (@Tjmax)
550 V
RDS(on) max.
< 0.19 Ω
ID 17 A
■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance
Application
Switching applications
Description
These devices are made using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a new vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
3 2 1
TO-220FP
3 2 1
TO-220
3 2 1
TO-247
3 1
D²PAK
Figure 1. Internal schematic diagram
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Table 1. Device summary Order codes STB23NM50N STF23NM50N STP23NM50N STW23NM50N
Marking 23NM50N
Package D²PAK
TO-220FP TO-220 TO-247
!-V
Packaging Tape and reel
Tube
May 2011
Doc ID 16913 Rev 4
1/21
www.st.com
21
Contents
Contents
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/21 Doc ID 16913 Rev 4
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
1 Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value Unit
TO-220, D²PAK TO-247 TO-220FP
VDS Drain-source voltage (VGS = 0)
VGS Gate- source voltage
ID Drain current (continuous) at TC = 25 °C
ID Drain current (continuous) at TC = 100 °C IDM (2) Drain current (pulsed)
PTOT Total dissipation at TC = 25 °C
VISO dv/dt (3)
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s;TC=25 °C)
Peak diode recovery voltage slope
500 ± 25 17 11 68 125
15
Tstg Storage temperature Tj Max. operating junction temperature
-55 to 150 150
1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD ≤ 17 A, di/dt ≤ 400 A/µs, VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS
17 (1) 11 (1) 68 (1)
30
V V A A A W
2500
V
V/ns °C °C
Table 3. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case max
Rthj-pcb (1)
Thermal resistance junction-pcb minimum footprint
Rthj-amb
Thermal resistance junctionambient max
Tl
Maximum lead temperature for soldering purpose
1. When mounted on 1inch² FR-4 board, 2 oz Cu
D²PAK
Value Unit
TO-247 TO-220 TO-220FP
1 4.17 °C/W
30 °C/W
62.5 50
62.5 °C/W
300 °C
Table 4. Avalanche characteristics
Symbol
Parameter
Avalanche current, repetitive or not-repetitive IAR (pulse width limited by Tj Max)
Single pulse avalanche energy EAS (starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Doc ID 16913 Rev 4
Value 6
254
Unit A mJ 3/21
Electrical characteristics
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
2 Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Drain-source V(BR)DSS breakdown voltage
IDSS
IGSS VGS(th) RDS(on)
Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage
Static drain-source on resistance
Test conditions
Min. Typ. Max. Unit
ID = 1 mA, VGS = 0
VDS = max rating VDS = max rating, @125 °C
VGS = ± 25 V
VDS = VGS, ID = 250 µA VGS = 10 V, ID = 8.5 A
500 V
1 µA 100 µA
100 nA
23
4V
0.162 0.19 Ω
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss Coss Crss
Input capacitance Output capacitance Reverse transfer capacitance
Coss eq. (1)
Equivalent output capacitance
Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge
Rg Gate input resistance
VDS = 50 V, f = 1 MHz, VGS = 0
VGS = 0, VDS = 0 to 400 V
VDD = 400 V, ID = 17 A, VGS = 10 V, (see Figure 18) f=1 MHz Gate DC Bias=0 Test signal level=20 mV open drain
1330 - 84 -
4.8
pF pF pF
- 210 - pF
45 nC - 7 - nC
24 nC
- 4.6 - Ω
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS
4/21 Doc ID 16913 Rev 4
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
Electrical characteristics
Table 7. Switching times
Symbol
Parameter
td(on) tr
td(off) tf
Turn-on delay time Rise time Turn-off-delay time Fall time
Test conditions
VDD = 250 V, ID = 17 A RG = 4.7 Ω VGS = 10 V (see Figure.