Document
DDR2 SDRAM AVR201628 (128M X 16 ) AVR200856 (256M X 8 ) AVR200412 (512M X 4 )
Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Duplicate output strobe (RDQS) option for x8 • DLL to align DQ and DQS transitions with CK • 8 internal banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8192-cycle refresh • On-die termination (ODT) • Industrial temperature (IT) option • RoHS-compliant • Supports JEDEC clock jitter specification
Table 1: Key Timing Parameters
Options1
Marking
• Configuration
– 512 Meg x 4 (64 Meg x 4 x 8 banks)
512M4
– 256 Meg x 8 (32 Meg x 8 x 8 banks)
256M8
– 128 Meg x 16 (16 Meg x 16 x 8 banks)
128M16
• FBGA package (Pb-free) – x16
– 84-ball FBGA (11.5mm x 14mm) Rev. A
HG
• FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (11.5mm x 14mm) Rev. A
HG
• Timing – cycle time
– 2.5ns @ CL = 6 (DDR2-800)
-25
– 3.0ns @ CL = 4 (DDR2-667)
-3E
– 3.0ns @ CL = 5 (DDR2-667)
-3
– 3.75ns @ CL = 4 (DDR2-533)
-37E
– 5.0ns @ CL = 3 (DDR2-400)
-5E
• Self refresh
– Standard
None
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C) – Industrial (–40°C ≤ TC ≤ 95°C;
–40°C ≤ TA ≤ 85°C)
Revision
•
:A
None
IT
Note:
1. Not all options listed can be combined to
define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability.
Speed Grade -8G -6F -6G -5F -4D
CL = 3 400 400 400 400 400
Data Rate (MHz)
CL = 4
CL = 5
533 667
667 667
533 667
533 n/a
400 n/a
CL = 6 800 n/a n/a n/a n/a
tRC (ns) 55 54 55 55 55
Part Number
ASL - __ AVR____S
_XXXX
AV R
A-Link memory
Product code R: DDR2 SDRAM
Density 28: 128M 56: 256M 12: 512M 10: 1G 20: 2G Bit Organization 04: X4 08: X8 16: X16 32: X32
Operation Temperature Range: I: Industrial Others: Commercial
S-
-BE
Plating Type E: Pb- Free
Package B: FBGA
Speed Code 4 :DDR400 D:3-3-3 5: DDR500 F:4-4-4 6: DDR667 G:5-5-5 8: DDR800 H:6-6-6 10:DDR1066 J:7-7-7 Voltage S: 1.8V
Address size 04: 4M 08: 8M 16: 16M 32: 32M 64: 64M 28: 128M
State Diagram
Figure 2: Simplified State Diagram
OCD default
Setting MRS EMRS
(E)MRS
Initialization sequence
PRE Idle
all banks precharged
SR CKE_H
CKE_L
Self refreshing
REFRESH
Refreshing
CKE_H CKE_L
CKE_L
Automatic Sequence Command Sequence
ACT
CKE_L
Active powerdown
CKE_L
Activating
CKE_CLKE_H
Bank active
WRITE
WRITE
Precharge powerdown
CKE_L
ACT = ACTIVATE CKE_H = CKE HIGH, exit power-down or self refresh CKE_L = CKE LOW, enter power-down (E)MRS = (Extended) mode register set PRE = PRECHARGE PRE_A = PRECHARGE ALL READ = READ READ A = READ with auto precharge REFRESH = REFRESH SR = SELF REFRESH WRITE = WRITE WRITE A = WRITE with auto precharge
READ
READ
WRITE A
READ A
Writing
WRITE
READ.