74ACT00 Gate Datasheet

74ACT00 Datasheet, PDF, Equivalent


Part Number

74ACT00

Description

Quad 2-Input NAND Gate

Manufacture

Fairchild Semiconductor

Total Page 10 Pages
Datasheet
Download 74ACT00 Datasheet


74ACT00
January 2008
74AC00, 74ACT00
Quad 2-Input NAND Gate
Features
ICC reduced by 50%
Outputs source/sink 24mA
ACT00 has TTL-compatible inputs
General Description
The AC00/ACT00 contains four, 2-input NAND gates.
Ordering Information
Order
Number
Package
Number
Package Description
74AC00SC
74AC00SJ
74AC00MTC
74AC00PC
74ACT00SC
74ACT00SJ
74ACT00MTC
74ACT00PC
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
An, Bn
On
Description
Inputs
Outputs
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1
www.fairchildsemi.com

74ACT00
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
IIK
VI
IOK
VO
IO
ICC or IGND
TSTG
TJ
Supply Voltage
DC Input Diode Current
VI = –0.5V
VI = VCC + 0.5
DC Input Voltage
DC Output Diode Current
VO = –0.5V
VO = VCC + 0.5V
DC Output Voltage
DC Output Source or Sink Current
DC VCC or Ground Current per Output Pin
Storage Temperature
Junction Temperature
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to VCC + 0.5V
–20mA
+20mA
–0.5V to VCC + 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VI
VO
TA
V / t
V / t
Parameter
Supply Voltage
AC
ACT
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate, AC Devices:
VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
–40°C to +85°C
125mV/ns
125mV/ns
©1988 Fairchild Semiconductor Corporation
74AC00, 74ACT00 Rev. 1.4.1
2
www.fairchildsemi.com


Features 74AC00, 74ACT00 — Quad 2-Input NAND Ga te January 2008 74AC00, 74ACT00 Quad 2-Input NAND Gate Features ■ ICC redu ced by 50% ■ Outputs source/sink 24mA ■ ACT00 has TTL-compatible inputs G eneral Description The AC00/ACT00 conta ins four, 2-input NAND gates. Ordering Information Order Number Package Num ber Package Description 74AC00SC 74AC 00SJ 74AC00MTC 74AC00PC 74ACT00SC 74ACT 00SJ 74ACT00MTC 74ACT00PC M14A M14D MT C14 N14A M14A M14D MTC14 N14A 14-Lead Small Outline Integrated Circuit (SOIC) , JEDEC MS-012, 0.150" Narrow 14-Lead S mall Outline Package (SOP), EIAJ TYPE I I, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Lin e Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated C ircuit (SOIC), JEDEC MS-012, 0.150" Nar row 14-Lead Small Outline Package (SOP) , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), J.
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