Flash MCU. SAM7X512 Datasheet

SAM7X512 MCU. Datasheet pdf. Equivalent

Part SAM7X512
Description ARM-based Flash MCU
Feature ARM-based Flash MCU SAM7X512 / SAM7X256 / SAM7X128 SUMMARY DATASHEET Description The Atmel SAM7X512/.
Manufacture ATMEL
Datasheet
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ARM-based Flash MCU SAM7X512 / SAM7X256 / SAM7X128 SUMMARY D SAM7X512 Datasheet
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SAM7X512
ARM-based Flash MCU
SAM7X512 / SAM7X256 / SAM7X128
DATASHEET
Description
The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on
the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash
and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet
MAC, and a CAN controller. A complete set of system functions minimizes the number
of external components.
The embedded Flash memory can be programmed in-system via the JTAG-ICE
interface or via a parallel interface on a production programmer prior to mounting. Built-
in lock bits and a security bit protect the firmware from accidental overwrite and
preserve its confidentiality.
The SAM7X512/256/128 system controller includes a reset controller capable of
managing the power-on sequence of the microcontroller and the complete system.
Correct device operation can be monitored by a built-in brownout detector and a
watchdog running off an integrated RC oscillator.
By combining the ARM7TDMI® processor with on-chip Flash and SRAM, and a wide
range of peripheral functions, including USART, SPI, CAN controller, Ethernet MAC,
Timer Counter, RTT and analog-to-digital converters on a monolithic chip, the
SAM7X512/256/128 is a powerful device that provides a flexible, cost-effective solution
to many embedded control applications requiring communication over Ethernet, wired
CAN and ZigBee® wireless networks.
6120K–ATARM–11-Feb-14



SAM7X512
Features
Incorporates the ARM7TDMI ARM Thumb® Processor
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash
512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of
256 Bytes (Dual Plane)
256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)
128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)
Single Cycle Access at Up to 30 MHz in Worst Case Conditions
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
128 Kbytes (SAM7X512)
64 Kbytes (SAM7X256)
32 Kbytes (SAM7X128)
Memory Controller (MC)
Embedded Flash Controller, Abort Status and Misalignment Detection
Reset Controller (RSTC)
Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector
Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR)
Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
Power Management Controller (PMC)
Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention
Mode for General Purpose 2-wire UART Serial Communication
Periodic Interval Timer (PIT)
20-bit Programmable Counter plus 12-bit Interval Counter
Windowed Watchdog (WDT)
12-bit key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
Real-time Timer (RTT)
32-bit Free-running Counter with Alarm
Runs Off the Internal RC Oscillator
Two Parallel Input/Output Controllers (PIO)
Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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