Document
ARM-based Flash MCU
SAM7X512 / SAM7X256 / SAM7X128
SUMMARY DATASHEET
Description
The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, and a CAN controller. A complete set of system functions minimizes the number of external components. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Builtin lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The SAM7X512/256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. By combining the ARM7TDMI® processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN controller, Ethernet MAC, Timer Counter, RTT and analog-to-digital converters on a monolithic chip, the SAM7X512/256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring communication over Ethernet, wired CAN and ZigBee® wireless networks.
This is a summary document. The complete document is available on the Atmel website at www.atmel.com.
6120IS–ATARM–14-Nov-13
Features
Incorporates the ARM7TDMI ARM Thumb® Processor High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash 512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) 256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) 128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) Single Cycle Access at Up to 30 MHz in Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed 128 Kbytes (SAM7X512) 64 Kbytes (SAM7X256) 32 Kbytes (SAM7X128)
Memory Controller (MC) Embedded Flash Controller, Abort Status and Misalignment Detection
Reset Controller (RSTC) Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR) Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
Power Management Controller (PMC) Power Opti.