Smart SoC. DA14580 Datasheet

DA14580 SoC. Datasheet pdf. Equivalent


Part DA14580
Description Low Power Bluetooth Smart SoC
Feature DA14580 Low Power Bluetooth Smart 4.2 SoC FINAL General description  84 kB ROM The DA14580 inte.
Manufacture Dialog Semiconductor
Datasheet
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DA14580 Low Power Bluetooth Smart 4.2 SoC FINAL General de DA14580 Datasheet
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DA14580
DA14580
Bluetooth Low Energy 4.2 SoC
FINAL
General Description
42 kB System SRAM
The DA14580 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® low energy. It can be used as a standalone
application processor or as a data pump in hosted sys-
tems.
84 kB ROM
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1, P2 and P3 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
The DA14580 supports a flexible memory architecture
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application
battery cells
code, which can be updated over the air (OTA). The
10-bit ADC for battery voltage measurement
qualified Bluetooth low energy protocol stack is stored
in a dedicated ROM. All software runs on the ARM®
Cortex®-M0 processor via a simple scheduler.
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
The Bluetooth low energy firmware includes the
L2CAP service layer protocols, Security Manager
(SM), Attribute Protocol (ATT), the Generic Attribute
Profile (GATT) and the Generic Access Profile (GAP).
All profiles published by the Bluetooth SIG as well as
custom profiles are supported.
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
General purpose I/Os: 14 (WLCSP34 package),
24 (QFN40 package), 32 (QFN48 package)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
The transceiver interfaces directly to the antenna and
I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.2 standard.
3-axes capable Quadrature Decoder
The DA14580 has dedicated hardware for the Link
Layer implementation of Bluetooth low energy and
interface controllers for enhanced connectivity capabili-
ties.
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
Features
switching required
Supply current at VBAT3V:
Complies with Bluetooth V4.2, ETSI EN 300 328 and
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
0 dBm transmit output power
(US) and ARIB STD-T66 (Japan)
-20 dBm output power in “Near Field Mode”
Processing power
-93 dBm receiver sensitivity
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
Packages:
face WLCSP 34 pins, 2.436 mm x 2.436 mm
Dedicated Link Layer Processor
QFN 40 pins, 5 mm x 5 mm
AES-128 bit encryption Processor
QFN 48 pins, 6 mm x 6 mm
Memories
KGD (wafer, dice)
32 kB One-Time-Programmable (OTP) memory
________________________________________________________________________________________________
System Diagram
Datasheet
CFR0011-120-01
Revision 3.4
1 of 234
09-Nov-2016
© 2014 Dialog Semiconductor



DA14580
DA14580
Bluetooth Low Energy 4.2 SoC
FINAL
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 9
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 INTERNAL BLOCKS . . . . . . . . . . . . . . . . . . . . 10
4.2 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 10
4.3 OTP MEMORY LAYOUT . . . . . . . . . . . . . . . . .11
4.3.1 OTP Header. . . . . . . . . . . . . . . . . . . . . . .11
4.4 SYSTEM START PROCEDURE . . . . . . . . . . . 12
4.4.1 Power/Wake-Up Sequence . . . . . . . . . . 13
4.4.2 OTP Mirroring . . . . . . . . . . . . . . . . . . . . 14
4.4.3 BootROM Sequence . . . . . . . . . . . . . . . 15
4.5 POWER SUPPLY CONFIGURATION . . . . . . 17
4.5.1 Power Domains . . . . . . . . . . . . . . . . . . . 17
4.5.2 Power Modes . . . . . . . . . . . . . . . . . . . . . 18
4.5.3 Retention Registers . . . . . . . . . . . . . . . . 18
5 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 POR, HW AND SW RESET . . . . . . . . . . . . . . 20
6 ARM Cortex-M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 SYSTEM TIMER (SYSTICK). . . . . . . . . . . . . . 23
6.3 WAKE-UP INTERRUPT CONTROLLER. . . . . 23
6.4 REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 AMBA Bus Overview. . . . . . . . . . . . . . . . . . . . . . . . 24
8 Patch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . 28
11 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1 CRYSTAL OSCILLATORS . . . . . . . . . . . . . . 29
11.1.1 Frequency Control (16 MHz Crystal) . . 29
11.1.2 Automated Trimming Mechanism . . . . 29
11.2 RC OSCILLATORS . . . . . . . . . . . . . . . . . . . . 30
11.2.1 Frequency Calibration . . . . . . . . . . . . . 30
11.3 SYSTEM CLOCK GENERATION . . . . . . . . . 31
11.4 GENERAL CLOCK CONSTRAINTS . . . . . . . 32
12 OTP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.1 OPERATING MODES . . . . . . . . . . . . . . . . . . 33
12.2 AHB MASTER INTERFACE . . . . . . . . . . . . . 33
13 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13.1 I2C BUS TERMS . . . . . . . . . . . . . . . . . . . . . . 34
13.1.1 Bus Transfer Terms . . . . . . . . . . . . . . . 35
13.2 I2C BEHAVIOR . . . . . . . . . . . . . . . . . . . . . . . 35
13.2.1 START and STOP Generation . . . . . . . 36
13.2.2 Combined Formats . . . . . . . . . . . . . . . 36
13.3 I2C PROTOCOLS . . . . . . . . . . . . . . . . . . . . . 36
13.3.1 START and STOP Conditions . . . . . . . 36
13.3.2 Addressing Slave Protocol. . . . . . . . . . 36
13.3.3 Transmitting and Receiving Protocols . 37
13.4 MULTIPLE MASTER ARBITRATION . . . . . . 39
13.5 CLOCK SYNCHRONIZATION . . . . . . . . . . . 40
13.6 OPERATION MODES . . . . . . . . . . . . . . . . . . 41
13.6.1 Slave Mode Operation . . . . . . . . . . . . . 41
13.6.2 Master Mode Operation . . . . . . . . . . . . 43
13.6.3 Disabling the I2C Controller . . . . . . . . . 43
14 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.1 UART (RS232) SERIAL PROTOCOL . . . . . . 45
14.2 IRDA 1.0 SIR PROTOCOL . . . . . . . . . . . . . . 45
14.3 CLOCK SUPPORT . . . . . . . . . . . . . . . . . . . . 46
14.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . 47
14.5 PROGRAMMABLE THRE INTERRUPT . . . . 47
14.6 SHADOW REGISTERS . . . . . . . . . . . . . . . . 49
14.7 DIRECT TEST MODE . . . . . . . . . . . . . . . . . . 49
15 SPI+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.1 OPERATION WITHOUT FIFOS . . . . . . . . . . 50
15.2 9 BITS MODE . . . . . . . . . . . . . . . . . . . . . . . . 51
16 Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . 54
17 Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
18 General Purpose Timers. . . . . . . . . . . . . . . . . . . . 56
18.1 TIMER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
18.2 TIMER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 60
20 Keyboard Controller . . . . . . . . . . . . . . . . . . . . . . . 61
20.1 KEYBOARD SCANNER . . . . . . . . . . . . . . . . 61
20.2 GPIO INTERRUPT GENERATOR . . . . . . . . 61
Datasheet
CFR0011-120-01
Revision 3.4
2 of 234
09-Nov-2016
© 2014 Dialog Semiconductor







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