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Data Selector/Multiplexer. 74S253 Datasheet

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Data Selector/Multiplexer. 74S253 Datasheet






74S253 Selector/Multiplexer. Datasheet pdf. Equivalent




74S253 Selector/Multiplexer. Datasheet pdf. Equivalent





Part

74S253

Description

Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer



Feature


DM74S253 Dual 3-STATE 1-of-4 Line Data S elector/Multiplexer August 1986 Revise d May 2000 DM74S253 Dual 3-STATE 1-of- 4 Line Data Selector/Multiplexer Gener al Description Each of these Schottky-c lamped data selectors/multiplexers cont ains inverters and drivers to supply fu lly complementary, on-chip, binary deco ding data selection to the AND-OR gates . Separate output .
Manufacture

Fairchild Semiconductor

Datasheet
Download 74S253 Datasheet


Fairchild Semiconductor 74S253

74S253; control inputs are provided for each of the two four-line sections. The 3-STATE outputs can interface directly with da ta lines of bus-organized systems. With all but one of the common outputs disa bled (at a high impedance state), the l ow impedance of the single enable outpu t will drive the bus line to a HIGH or LOW logic level. Features s 3-STATE ve rsion of S153 with.


Fairchild Semiconductor 74S253

same pin-out s Schottky-diode-clamped t ransistors s Permits multiplexing from N lines to 1 line s Performs parallel-T -serial conversion s Strobe/output cont rol s High fan-out totem-pole outputs s Typical propagation delay From data to output 6 ns From select to output 12 n s s Typical power dissipation 275 mW O rdering Code: Order Number Package Num ber Package Descr.


Fairchild Semiconductor 74S253

iption DM74S253N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS- 001, 0.300 Wide Connection Diagram Fu nction Table Select Data Inputs Outp ut Inputs Control B A C0 C1 C2 C3 G XXXXXX H L L LXXX L L LHXXX L L HX L XX L LHXHXX L HLXXLX L H L XXHX L HHXXX L L HHXXXH L Address inputs A and B are common to both sect ions. H = HIGH Lev.

Part

74S253

Description

Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer



Feature


DM74S253 Dual 3-STATE 1-of-4 Line Data S elector/Multiplexer August 1986 Revise d May 2000 DM74S253 Dual 3-STATE 1-of- 4 Line Data Selector/Multiplexer Gener al Description Each of these Schottky-c lamped data selectors/multiplexers cont ains inverters and drivers to supply fu lly complementary, on-chip, binary deco ding data selection to the AND-OR gates . Separate output .
Manufacture

Fairchild Semiconductor

Datasheet
Download 74S253 Datasheet




 74S253
August 1986
Revised May 2000
DM74S253
Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
General Description
Each of these Schottky-clamped data selectors/multiplex-
ers contains inverters and drivers to supply fully comple-
mentary, on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are pro-
vided for each of the two four-line sections.
The 3-STATE outputs can interface directly with data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high impedance state), the low
impedance of the single enable output will drive the bus
line to a HIGH or LOW logic level.
Features
s 3-STATE version of S153 with same pin-out
s Schottky-diode-clamped transistors
s Permits multiplexing from N lines to 1 line
s Performs parallel-T-serial conversion
s Strobe/output control
s High fan-out totem-pole outputs
s Typical propagation delay
From data to output 6 ns
From select to output 12 ns
s Typical power dissipation 275 mW
Ordering Code:
Order Number Package Number
Package Description
DM74S253N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Select
Data Inputs
Output
Inputs
Control
B A C0 C1 C2 C3
G
XXXXXX
H
L L LXXX
L
L LHXXX
L
L HX L XX
L
LHXHXX
L
HLXXLX
L
H L XXHX
L
HHXXX L
L
HHXXXH
L
Address inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don’t Care
Z = High Impedance
Output
Y
Z
L
H
L
H
L
H
L
H
© 2000 Fairchild Semiconductor Corporation DS006481
www.fairchildsemi.com




 74S253
Logic Diagram
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2




 74S253
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 1: The Absolute Maximum Ratingsare those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditionstable will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
Min Nom
4.75 5
2
0
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
Output Voltage
VCC = Min, IOH = Max
VIL = Max, VIH = Min
2.4
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II
Input Current @ Max Input Voltage
VCC = Max, VI = 5.5V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL Low Level Input Current
VCC = Max, VI = 0.5V
IOZH
Off-State Output Current with
VCC = Max, VO = 2.4V
HIGH Level Output Voltage Applied
VIH = Min, VIL = Max
IOZL Off-State Output Current with
VCC = Max, VO = 0.5V
LOW Level Output Voltage Applied
VIH = Min, VIL = Max
IOS Short Circuit Output Current
VCC = Max (Note 3)
40
ICC Supply Current
VCC = Max (Note 4)
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: ICC is measured with all outputs OPEN.
Max
5.25
0.8
6.5
20
70
Units
V
V
V
mA
mA
°C
Typ
(Note 2)
3.2
55
Max
1.2
0.5
1
50
2
50
50
100
70
Units
V
V
V
mA
µA
mA
µA
µA
mA
mA
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
From (Input)
To (Output)
tPLH
Propagation Delay Time LOW-to-HIGH Level Output
Data to Y
tPHL
Propagation Delay Time HIGH-to-LOW Level Output
Data to Y
tPLH Propagation Delay Time LOW-to-HIGH Level Output Select to Y
tPHL Propagation Delay Time HIGH-to-LOW Level Output Select to Y
tPZH Output Enable Time to HIGH Level Output
Output Control to Y
tPZL Output Enable Time to LOW Level Output
Output Control to Y
tPHZ Output Disable Time to HIGH Level Output (Note 5) Output Control to Y
tPLZ Output Disable Time to LOW Level Output (Note 5) Output Control to Y
Note 5: CL = 5 pF.
RL = 280
CL = 15 pF
CL = 50 pF
Min Max Min Max
9 12
9 12
18 21
18 21
16.5
19.5
18 21
9.5
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
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