Document
APT75F50B2 APT75F50L
500V, 75A, 0.075Ω Max, trr ≤310ns
N-Channel FREDFET
Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. This 'FREDFET' version has a drain-source (body) diode that has been optimized for high reliability in ZVS phase shifted bridge and other circuits through reduced trr, soft recovery, and high recovery dv/dt capability. Low gate charge, high gain, and a greatly reduced ratio of Crss/Ciss result in excellent noise immunity and low switching loss. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control di/dt during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency.
T-Max®
TO-264
APT75F50B2 APT75F50L Single die FREDFET G
D S
FEATURES
• Fast switching with low EMI
• Low trr for high reliability • Ultra low Crss for improved noise immunity • Low gate charge
• Avalanche energy rated • RoHS compliant
TYPICAL APPLICATIONS
• ZVS phase shifted and other full bridge • Half bridge • PFC and other boost converter • Buck converter • Single and two switch forward • Flyback
Absolute Maximum Ratings Symbol Parameter
ID
Continuous Drain Current @ TC = 25°C Continuous Drain Current @ TC = 100°C
IDM Pulsed Drain Current 1
VGS Gate-Source Voltage
EAS Single Pulse Avalanche Energy 2
IAR Avalanche Current, Repetitive or Non-Repetitive
Thermal and Mechanical Characteristics
Symbol Characteristic
PD RθJC RθCS TJ,TSTG
Total Power Dissipation @ TC = 25°C Junction to Case Thermal Resistance
Case to Sink Thermal Resistance, Flat, Greased Surface Operating and Storage Junction Temperature Range
TL Soldering Temperature for 10 Seconds (1.6mm from case)
WT Package Weight
Torque Mounting Torque ( TO-264Package), 4.40 or M3 screw
Ratings
Unit
75
47
A
230
±30
V
1580
mJ
37
A
Min Typ
0.11
-55
0.22
6.2
Max 1040 0.12
150 300
10 1.1
Unit W
°C/W
°C
oz g in·lbf N·m
MicrosemiWebsite-http://www.microsemi.com
050-8126 Rev C 05-2009
Static Characteristics
TJ = 25°C unless otherwise specified
APT75F50B2_L
Symbol Parameter
Test Conditions
Min Typ Max Unit
VBR(DSS) ∆VBR(DSS)/∆TJ
RDS(on) VGS(th)
∆VGS(th)/∆TJ
Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Drain-Source On Resistance 3 Gate-Source Threshold Voltage Threshold Voltage Temperature Coefficient
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 250µA
VGS = 10V, ID = 37A
VGS = VDS, ID = 2.5mA
500
0.60
0.064
2.5
4
-10
0.075 5
V V/°C
Ω V mV/°C
IDSS Zero Gate Voltage Drain Current
VDS = 500V VGS = 0V
TJ = 25°C TJ = 125°C
250 1000
µA
IGSS Gate-Source Leakage Current
VGS = ±30V
±100 nA
Dynamic Characteristics
Symbol gfs
Ciss Crss Coss
Parameter Forward Transconductance Input Capacitance Reverse Transfer Capacitance Output Capacitance
TJ = 25°C unless otherwise specified
Test Conditions
Min
VDS = 50V, ID = 37A
VGS = 0V, VDS = 25V
f = 1MHz
Co(cr) 4 Co(er) 5
Effective Output Capacitance, Charge Related Effective Output Capacitance, Energy Related
VGS = 0V, VDS = 0V to 333V
Qg Qgs Qgd td(on)
tr td(off)
tf
Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Current Rise Time Turn-Off Delay Time Current Fall Time
VGS = 0 to 10V, ID = 37A,
VDS = 250V
Resistive Switching
VDD = 333V, ID = 37A RG = 2.2Ω 6 , VGG = 15V
Typ 55 11600 160 1250
725
365
290 65 130 45 55 120 39
Max
Unit S
pF
nC ns
Source-Drain Diode Characteristics
Symbol Parameter
IS
Continuous Source Current (Body Diode)
ISM
Pulsed Source Current (Body Diode) 1
VSD Diode Forward Voltage
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Irrm Reverse Recovery Current
dv/dt
Peak Recovery dv/dt
Test Conditions
Min Typ
MOSFET symbol showing the integral reverse p-n junction diode (body diode)
D
G
S
ISD = 37A, TJ = 25°C, VGS = 0V
ISD = 37A 3
TJ = 25°C TJ = 125°C TJ = 25°C
1.48
VDD = 100V
diSD/dt = 100A/µs
TJ = 125°C TJ = 25°C
3.85 11.3
TJ = 125°C
16.6
ISD ≤ 37A, di/dt ≤1000A/µs, VDD = TJ = 125°C
333V,
Max 75 230 1.0 310 570
20
Unit
A
V ns µC A V/ns
050-8126 Rev C 05-2009
1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 2.31mH, RG = 25Ω, IAS = 37A. 3 Pulse test: Pulse Width < 380µs, duty cycle < 2%.
4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.65E-7/VDS^2 + 5.51E-8/VDS + 2.03E-10. 6 RG is external gate resistance, not including internal gate.