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Buck Controller. NCP3218 Datasheet

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Buck Controller. NCP3218 Datasheet






NCP3218 Controller. Datasheet pdf. Equivalent




NCP3218 Controller. Datasheet pdf. Equivalent





Part

NCP3218

Description

Mobile CPU Synchronous Buck Controller



Feature


ADP3212, NCP3218, NCP3218G 7-Bit, Progr ammable, 3-Phase, Mobile CPU Synchronou s Buck Controller The APD3212/NCP3218/ NCP3218G is a highly efficient, multi∠’phase, synchronous buck switching regu lator controller. With http://onsemi.c om its integrated drivers, the APD3212 /NCP3218/NCP3218G is optimized for con verting the notebook battery voltage in to the core supply .
Manufacture

ON Semiconductor

Datasheet
Download NCP3218 Datasheet


ON Semiconductor NCP3218

NCP3218; voltage required by high performance Int el processors. An internal 7−bit DAC is used to read a VID code directly fr om the processor and to set the CPU cor e voltage to a value within the range 1 48 1 48 of 0.3 V to 1.5 V. The APD3 212/NCP3218/NCP3218G is QFN48 QFN48 programmable for 1−, 2−, or 3−pha se operation. The output signals CASE 485AJ CASE 485BA ensure .


ON Semiconductor NCP3218

interleaved 2− or 3−phase operation. The APD3212/NCP3218/NCP3218G uses a mu ltimode architecture run at a programma ble switching frequency and optimized f or efficiency depending on the output c urrent requirement. The APD3212/NCP3218 /NCP3218G switches between single− an d multi−phase operation to maximize e fficiency with all load conditions. MA RKING DIAGRAM 1 xxx = Sp.


ON Semiconductor NCP3218

ecific Device Code (ADP3212 or NCP3218/ G) xxP321x A = Assembly Location AWL YYWWG WL = Wafer Lot The chip includes a programmable load line slope functio n to adjust the output voltage as a fun ction of the load current so that the c ore voltage is always optimally positio ned for a load transient. The APD3212/ YY = Year WW = Work Week G = Pb−Free Package NCP3218/NC.

Part

NCP3218

Description

Mobile CPU Synchronous Buck Controller



Feature


ADP3212, NCP3218, NCP3218G 7-Bit, Progr ammable, 3-Phase, Mobile CPU Synchronou s Buck Controller The APD3212/NCP3218/ NCP3218G is a highly efficient, multi∠’phase, synchronous buck switching regu lator controller. With http://onsemi.c om its integrated drivers, the APD3212 /NCP3218/NCP3218G is optimized for con verting the notebook battery voltage in to the core supply .
Manufacture

ON Semiconductor

Datasheet
Download NCP3218 Datasheet




 NCP3218
ADP3212, NCP3218,
NCP3218G
7-Bit, Programmable,
3-Phase, Mobile CPU
Synchronous Buck Controller
The APD3212/NCP3218/NCP3218G is a highly efficient,
multi−phase, synchronous buck switching regulator controller. With
http://onsemi.com
its integrated drivers, the APD3212/NCP3218/NCP3218G is
optimized for converting the notebook battery voltage into the core
supply voltage required by high performance Intel processors. An
internal 7−bit DAC is used to read a VID code directly from the
processor and to set the CPU core voltage to a value within the range
1 48
1 48
of 0.3 V to 1.5 V. The APD3212/NCP3218/NCP3218G is
QFN48
QFN48
programmable for 1−, 2−, or 3−phase operation. The output signals
CASE 485AJ
CASE 485BA
ensure interleaved 2− or 3−phase operation.
The APD3212/NCP3218/NCP3218G uses a multimode architecture
run at a programmable switching frequency and optimized for
efficiency depending on the output current requirement. The
APD3212/NCP3218/NCP3218G switches between single− and
multi−phase operation to maximize efficiency with all load conditions.
MARKING DIAGRAM
1
xxx = Specific Device Code
(ADP3212 or NCP3218/G)
xxP321x
A = Assembly Location
AWLYYWWG WL = Wafer Lot
The chip includes a programmable load line slope function to adjust the
output voltage as a function of the load current so that the core voltage is
always optimally positioned for a load transient. The APD3212/
YY = Year
WW = Work Week
G = Pb−Free Package
NCP3218/NCP3218G also provides accurate and reliable short−circuit
protection, adjustable current limiting, and a delayed power−good
ORDERING INFORMATION
output. The IC supports On−The−Fly (OTF) output voltage changes
requested by the CPU.
See detailed ordering and shipping information in the package
dimensions section on page 33 of this data sheet.
The APD3212/NCP3218/NCP3218G are specified over
the extended commercial temperature range of −40°C to
100°C. The ADP3212 is available in a 48−lead QFN 7x7mm
0.5mm pitch package. The NCP3218/NCP3218G is
available in a 48−lead QFN 6x6mm 0.4mm pitch package.
ADP3212/NCP3218 has 1.1 V Vboot Voltage, while
NCP3218G has 987.5 mV Vboot Voltage. Except for the
packages and Vboot Voltages, the APD3212/NCP3218/
NCP3218G are identical. APD3212/NCP3218/NCP3218G
• Active Current Balancing Between Output Phases
• Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
• Built−In Power−Good Blanking Supports Voltage
Identification (VID) On−The−Fly (OTF) Transients
• 7−Bit, Digitally Programmable DAC with 0.3 V to
1.5 V Output
• Short−Circuit Protection with Programmable Latchoff
are Halogen−Free, Pb−Free and RoHS compliant.
Delay
Features
• Single−Chip Solution
• Fully Compatible with the Intel® IMVP−6.5t
Specifications
• Selectable 1−, 2−, or 3−Phase Operation with Up to 1
MHz per Phase Switching Frequency
• Phase 1 and Phase 2 Integrated MOSFET Drivers
• Input Voltage Range of 3.3 V to 22 V
• Guaranteed ±8 mV Worst−Case Differentially Sensed
• Clock Enable Output Delays the CPU Clock Until the
Core Voltage is Stable
• Output Power or Current Monitor Options
• 48−Lead QFN 7x7mm (ADP3212), 48−Lead QFN
6x6mm (NCP3218/NCP3218G)
• Vboot = 1.1 V (ADP3212/NCP3218)
Vboot = 987.5 mV (NCP3218G)
• These are Pb−Free Devices
• Fully RoHS Compliant
Core Voltage Error Over Temperature
Applications
• Automatic Power−Saving Mode Maximizes Efficiency
• Notebook Power Supplies for Next−Generation Intel
with Light Load During Deeper Sleep Operation
Processors
© Semiconductor Components Industries, LLC, 2012
August, 2012 − Rev. 4
1
Publication Order Number:
ADP3212/D




 NCP3218
ADP3212, NCP3218, NCP3218G
PIN ASSIGNMENT
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
TRDET
VARFREQ
VRTT
TTSNS
GND
1
ADP3212
NCP3218
(top view)
BST1
DRVH1
SW1
SWFB1
PVCC
DRVL1
PGND
DRVL2
SWFB2
SW2
DRVH2
BST2
GND
VCC EN RPM RT RAMP VARFREQ
TRDET
COMP
FB
LLINE
SWFB1
SWFB2
SWFB3
PH0
PH1
PWRGD
CLKEN
FBRTN
GTeRneDrEatTor
UVLO
Shutdown
and Bias
Oscillator
+S
REF +
VEA
−
+
CSREF
+S _
1.55 V
Current
Balancing
Circuit
OVP
Driver
Logic
DAC + 200 mV
CSREF
+−
−
+
DAC − 300 mV
PWRGD
Open
Drain
CLKEN
Open
Drain
Precision
Reference
Number of
Phases
OCP
Shutdown
Delay
PWRGD
Start Up
Delay
CLKEN
Start Up
Delay
Current
Limit
Circuit
Soft
Transient
Delay
Delay
Disable
VID
DAC
DAC
REF
PVCC
PGND
PSI and
DPRSLP
Logic
CCuurrerennt t
MMoonnitiotor r
+
−
Thermal
Throttle
Control
Soft Start
BST1
DRVH1
SW1
PVCC
DRVL1
PGND
BST2
DRVH2
SW2
DRVL2
OD3
PWM3
PSI
DPRSLP
IMON
CSREF
CSSUM
CSCOMP
ILIM
TTSENSE
VRTT
Figure 1. Functional Block Diagram
http://onsemi.com
2




 NCP3218
ADP3212, NCP3218, NCP3218G
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
VCC, PVCC1, PVCC2
FBRTN, PGND1, PGND2
−0.3 to +6.0
−0.3 to +0.3
V
V
BST1, BST2, DRVH1, DRVH2
DC
t < 200 ns
−0.3 to +28
−0.3 to +33
V
BST1 to PVCC, BST2 to PVCC
DC
t < 200 ns
−0.3 to +22
−0.3 to +28
V
BST1 to SW1, BST2 to SW2
−0.3 to +6.0
V
SW1, SW2
DC
t < 200 ns
−1.0 to +22
−6.0 to +28
V
DRVH1 to SW1, DRVH2 to SW2
−0.3 to +6.0
V
DRVL1 to PGND1, DRVL2 to PGND2
DC
t < 200 ns
−0.3 to +6.0
−5.0 to +6.0
V
RAMP (in Shutdown)
−0.3 to +22
V
All Other Inputs and Outputs
−0.3 to +6.0
V
Storage Temperature Range
−65 to +150
°C
Operating Ambient Temperature Range
−40 to +100
°C
Operating Junction Temperature
125 °C
Thermal Impedance (qJA) 2−Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
30.5 °C/W
°C
300
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
PIN ASSIGNMENT
Pin No. Mnemonic
1 EN
2 PWRGD
3 IMON
4 CLKEN
5 FBRTN
6 FB
7 COMP
8 TRDET
9 VARFREQ
10 VRTT
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and
VRTT low, and pulls CLKEN high.
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to
the external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive
load transients at high frequencies, this circuit optimally positions the maximum and minimum output
voltage into a specified loadline window.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
http://onsemi.com
3



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