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NAND Gate. 74HC133 Datasheet

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NAND Gate. 74HC133 Datasheet






74HC133 Gate. Datasheet pdf. Equivalent




74HC133 Gate. Datasheet pdf. Equivalent





Part

74HC133

Description

13-Input NAND Gate



Feature


MM54HC133 MM74HC133 13-Input NAND Gate January 1988 MM54HC133 MM74HC133 13-In put NAND Gate General Description This NAND gate utilizes advanced silicon-ga te CMOS technology to achieve operating speeds similar to LS-TTL gates with th e low power consumption of standard CMO S integrated circuits All gates have bu ffered outputs All devices have high no ise immunity and t.
Manufacture

National Semiconductor

Datasheet
Download 74HC133 Datasheet


National Semiconductor 74HC133

74HC133; he ability to drive 10 LS-TTL loads The 54HC 74HC logic family is functionally as well as pin-out compatible with the standard 54LS 74LS logic family All inp uts are protected from damage due to st atic discharge by internal diode clamps to VCC and ground Features Y Typical propagation delay 20 ns Y Wide power su pply range 2 – 6V Y Low quiescent cur rent 20 mA maximum (.


National Semiconductor 74HC133

74HC Series) Y Low input current 1 mA ma ximum Y Fanout of 10 LS-TTL loads Conn ection and Logic Diagrams Dual-In-Line Package Top View Order Number MM54HC13 3 or MM74HC133 TL F 5134 – 1 C1995 National Semiconductor Corporation TL F 5134 TL F 5134 – 2 RRD-B30M105 Prin ted in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace spec ified devices are requ.


National Semiconductor 74HC133

ired please contact the National Semicon ductor Sales Office Distributors for av ailability and specifications Supply V oltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Curre nt (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (I CC) Storage Temperature Range (TSTG) Po wer Dissipation (PD) (Note 3) S O Packa ge only b0 5 to a.

Part

74HC133

Description

13-Input NAND Gate



Feature


MM54HC133 MM74HC133 13-Input NAND Gate January 1988 MM54HC133 MM74HC133 13-In put NAND Gate General Description This NAND gate utilizes advanced silicon-ga te CMOS technology to achieve operating speeds similar to LS-TTL gates with th e low power consumption of standard CMO S integrated circuits All gates have bu ffered outputs All devices have high no ise immunity and t.
Manufacture

National Semiconductor

Datasheet
Download 74HC133 Datasheet




 74HC133
January 1988
MM54HC133 MM74HC133 13-Input NAND Gate
General Description
This NAND gate utilizes advanced silicon-gate CMOS tech-
nology to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS inte-
grated circuits All gates have buffered outputs All devices
have high noise immunity and the ability to drive 10 LS-TTL
loads The 54HC 74HC logic family is functionally as well as
pin-out compatible with the standard 54LS 74LS logic fami-
ly All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground
Features
Y Typical propagation delay 20 ns
Y Wide power supply range 2 – 6V
Y Low quiescent current 20 mA maximum (74HC Series)
Y Low input current 1 mA maximum
Y Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Top View
Order Number MM54HC133 or MM74HC133
TL F 5134 – 1
C1995 National Semiconductor Corporation TL F 5134
TL F 5134 – 2
RRD-B30M105 Printed in U S A




 74HC133
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK IOK)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g25 mA
g50 mA
b65 C to a150 C
600 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage VCC
DC Input or Output Voltage
VIN VOUT
Operating Temp Range (TA)
MM HC
MM HC
Min
b
b
Input Rise or Fall Times
tr tf VCCe V
VCCe V
VCCe V
Max
VCC
a
a
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level
Input Voltage
V
V
V
V
V
V
VIL Maximum Low Level
Input Voltage
V
V
V
V
V
V
VOH
Minimum High Level VINeVIH or VIL
Output Voltage
lIOUTls mA
V
V
V
V
V
V
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
VOL Maximum Low Level VINeVIH
Output Voltage
lIOUTls mA
V
V
V
V
V
V
V
V
V
V
VINeVIH
lIOUTls mA
lIOUTls mA
V
V
IIN
Maximum Input
VINeVCC or GND
V
Current
g
g
V
V
g mA
ICC
Maximum Quiescent VINeVCC or GND
V
Supply Current
IOUTe mA
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and
IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2




 74HC133
AC Electrical Characteristics VCCe5V TAe25 C CLe15 pF tretfe6 ns
Symbol
Parameter
Conditions Typ Guaranteed Units
Limit
tPHL tPLH Maximum Propagation Delay
ns
AC Electrical Characteristics VCCe2 0V to 6 0V CLe50 pF tretfe6 ns (unless otherwise specified)
Symbol
Parameter
Conditions VCC
TAe25 C
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C Units
Typ Guaranteed Limits
tPHL
tPLH
Maximum Propagation
Delay
V
V
V
ns
ns
ns
tTLH
tTHL
Maximum
Output Rise and
Fall Time
V
V
V
ns
ns
ns
CPD Power Dissipation
Capacitance Note
pF
CIN Maximum Input Capacitance
pF
Note 5 CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC133J or MM74HC133J
NS Package Number J16A
3



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