XC3S5000 FPGA Datasheet

XC3S5000 Datasheet, PDF, Equivalent


Part Number

XC3S5000

Description

Spartan-3 FPGA

Manufacture

Xilinx

Total Page 30 Pages
Datasheet
Download XC3S5000 Datasheet


XC3S5000
1
DS099 June 27, 2013
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
• Introduction
• Features
• Architectural Overview
• Array Sizes and Resources
• User I/O Chart
• Ordering Information
Module 2: Functional Description
DS099 (v3.1) June 27, 2013
• Input/Output Blocks (IOBs)
• IOB Overview
• SelectIO™ Interface I/O Standards
• Configurable Logic Blocks (CLBs)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• DC Characteristics
• Switching Characteristics
• I/O Timing
• Internal Logic Timing
• DCM Timing
• Configuration and JTAG Timing
Spartan-3 FPGA Family
Data Sheet
Product Specification
Module 4: Pinout Descriptions
DS099 (v3.1) June 27, 2013
• Pin Descriptions
• Pin Behavior During Configuration
• Package Overview
• Pinout Tables
• Footprints
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS099 June 27, 2013
Product Specification
www.xilinx.com
1

XC3S5000
8
Spartan-3 FPGA Family:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
Introduction
The Spartan®-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
5,000,000 system gates, as shown in Table 1.
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex®-II platform
technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more
functionality and bandwidth per dollar than was previously
possible, setting new standards in the programmable logic
industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection and digital television
equipment.
The Spartan-3 family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Table 1: Summary of Spartan-3 FPGA Attributes
Device
XC3S50(2)
XC3S200 (2)
XC3S400 (2)
XC3S1000 (2)
System
Gates
CLB Array
Equivalent (One CLB = Four Slices)
Logic Cells(1)
Rows Columns
Total
CLBs
50K 1,728 16 12 192
200K
4,320
24
20
480
400K
8,064
32
28
896
1M
17,280
48
40 1,920
XC3S1500
1.5M
29,952
64
52 3,328
XC3S2000
2M
46,080
80
64 5,120
XC3S4000
4M
62,208
96
72 6,912
XC3S5000
5M
74,880
104
80
8,320
Features
• Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
• Densities up to 74,880 logic cells
• SelectIO™ interface signaling
• Up to 633 I/O pins
• 622+ Mb/s data transfer rate per I/O
• 18 single-ended signal standards
• 8 differential I/O standards including LVDS, RSDS
• Termination by Digitally Controlled Impedance
• Signal swing ranging from 1.14V to 3.465V
• Double Data Rate (DDR) support
DDR, DDR2 SDRAM support up to 333 Mb/s
• Logic resources
• Abundant logic cells with shift register capability
• Wide, fast multiplexers
• Fast look-ahead carry logic
• Dedicated 18 x 18 multipliers
• JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
• Up to 1,872 Kbits of total block RAM
• Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
• Clock skew elimination
• Frequency synthesis
• High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE® and WebPACK™ software
development systems
MicroBlaze™ and PicoBlaze™ processor, PCI®,
PCI Express® PIPE Endpoint, and other IP cores
• Pb-free packaging options
• Automotive Spartan-3 XA Family variant
Distributed
RAM Bits
(K=1024)
Block
RAM Bits
(K=1024)
Dedicated
Multipliers
DCMs
Max.
User I/O
Maximum
Differential
I/O Pairs
12K
30K
56K
120K
208K
320K
432K
520K
72K
216K
288K
432K
576K
720K
1,728K
1,872K
4
12
16
24
32
40
96
104
2 124
4 173
4 264
4 391
4 487
4 565
4 633
4 633
56
76
116
175
221
270
300
300
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS099 (v3.1) June 27, 2013
Product Specification
www.xilinx.com
2


Features 1 DS099 June 27, 2013 Module 1: Introduc tion and Ordering Information DS099 (v3 .1) June 27, 2013 • Introduction • Features • Architectural Overview • Array Sizes and Resources • User I/O Chart • Ordering Information Module 2: Functional Description DS099 (v3.1) June 27, 2013 • Input/Output Blocks ( IOBs) • IOB Overview • SelectIO™ Interface I/O Standards • Configurabl e Logic Blocks (CLBs) • Block RAM • Dedicated Multipliers • Digital Cloc k Manager (DCM) • Clock Network • C onfiguration Module 3: DC and Switching Characteristics DS099 (v3.1) June 27, 2013 • DC Electrical Characteristics • Absolute Maximum Ratings • Supply Voltage Specifications • Recommended Operating Conditions • DC Characteri stics • Switching Characteristics • I/O Timing • Internal Logic Timing DCM Timing • Configuration and JTA G Timing Spartan-3 FPGA Family Data Sh eet Product Specification Module 4: Pin out Descriptions DS099 (v3.1) June 27, 2013 • Pin Descriptions • Pin Behavior During Configuration • Package Overvi.
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