Delta-Sigma ADC. MAX11259 Datasheet

MAX11259 ADC. Datasheet pdf. Equivalent


Maxim Integrated MAX11259
MAX11259
EVALUATION KIT AVAILABLE
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
General Description
The MAX11259 is a 6-channel, 24-bit delta-sigma ADC
that achieves exceptional performance while consuming
very low power. Sample rates up to 16ksps allow preci-
sion DC measurements. The MAX11259 communicates
via an I2C-compatible serial interface and is available in a
small (3mm x 3mm) WLP package.
The MAX11259 offers a 6.2nV/Hz noise programmable
gain amplifier (PGA) with gain settings from 1x to 128x.
The integrated PGA provides isolation of the signal inputs
from the switched capacitor sampling network. The PGA
also enables the MAX11259 to interface directly with
high-impedance sources without compromising available
dynamic range.
The MAX11259 operates from a single 2.7V to 3.6V
analog supply, or split ±1.8V analog supplies, allowing
the analog input to be sampled below ground. The digital
supply range is 1.7V to 2.0V or 2.0V to 3.6V, allowing
communication with 1.8V, 2.5V, 3V, or 3.3V logic.
Applications
● Wearable Electronics
● Weigh Scales
● Pressure Sensors
● Battery-Powered Instrumentation
Typical Application Circuit
Benefits and Features
● High Resolution for Industrial Applications that
Require a Wide Dynamic Range
• 133dB SNR at 50sps
• 124dB SNR at 1000sps
● Longer Battery Life for Portable Applications
• 2.2mA Operating Mode Current
1μA Sleep Current
● Single or Split Analog Supplies Provide Input Voltage
Range Flexibility
• 2.7V to 3.6V (Single Supply) or ±1.8V (Split Supply)
● Enables System Integration
• Low Noise, 6.2nV/Hz PGA with Gains of 1, 2, 4,
8, 16, 32, 64, 128
• 6-Channel, Fully Differential Input
● Enables On-Demand Device and System Gain and
Offset Calibration
• User-Programmable Offset and Gain Registers
● Robust Performance in a Small Package
• -40°C to +125°C Operating Temperature Range
• WLP Package, 3mm x 3mm (6 x 6 Ball Array)
2.7V TO 3.6V
REF
10nF 1µF 2.0V TO 3.6V
1nF
C0G
AIN0N
AIN5P
1nF
C0G
AIN0P
REFN REFP
AVDD
MAX11259
DVDD
RSTB
ADR0
SCL
ADR1
SDA
RDYB
AIN5N
GPO0 GPO1 GPOGND CAPP CAPN CAPREG AVSS
220nF
0603
X7R
1nF
C0G
RESISTIVE BRIDGE MEASUREMENT CIRCUIT, I2C CONFIGURATION
DGND
1µF
µC
19-7749; Rev 0; 9/15


MAX11259 Datasheet
Recommendation MAX11259 Datasheet
Part MAX11259
Description Delta-Sigma ADC
Feature MAX11259; MAX11259 EVALUATION KIT AVAILABLE 24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA, Delta-Sigma ADC with I2.
Manufacture Maxim Integrated
Datasheet
Download MAX11259 Datasheet




Maxim Integrated MAX11259
MAX11259
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
Absolute Maximum Ratings
AVDD to AVSS......................................................-0.3V to +3.9V
AVDD to DGND.....................................................-0.3V to +3.9V
DVDD to DGND.....................................................-0.3V to +3.9V
AVSS to DGND...................................................-1.95V to +0.3V
DVDD to AVSS......................................................-0.3V to +3.9V
AVSS to GPOGND..............................................-1.95V to +0.3V
GPOGND to DGND.............................................-1.95V to +0.3V
AIN_P, AIN_N,REFP, REFN,
CAPP, CAPN to AVSS............................. -0.3V to the lower of
+3.9V or (VAVDD + 0.3V)
GPO_ to GPOGND..................................... -0.3V to the lower of
+3.9V or (VAVDD + 0.3V)
CAPREG to AVSS.................................................-0.3V to +3.9V
CAPREG to DGND................................................-0.3V to +2.1V
All Other Bumps to DGND.......................... -0.3V to the lower of
+3.9V or (VDVDD + 0.3V)
Maximum Continuous Current into Any Bumps
Except GPOGND Bump...............................................±50mA
Maximum Continuous Current into
GPOGND Bump..........................................................±100mA
Continuous Power Dissipation (TA = +70°C)
WLP (derate 26.3mW/°C above +70°C).....................2105mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -55°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (θJA)(Note 2)...38°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 2: Refer to Application Note 1891: Wafer-Level Packaging (WLP) and its Applications for information about the thermal
performance of WLP packaging.
Electrical Characteristics
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V to 3.6V, VREFP - VREFN = VAVDD, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
STATIC PERFORMANCE (Single-Cycle Conversion Mode)
Noise Voltage
(Referred to Input)
PGA low-
PGA gain of 128,
noise mode
single-cycle mode at
1ksps data rate
PGA low-
power mode
Vn
PGA gain of 128,
PGA low-
single-cycle
noise mode
mode at 12.8ksps
data rate
PGA low-
power mode
0.19
0.26
0.83
1.16
µVRMS
Integral Nonlinearity
INL
3 15 ppm
Zero Error
Zero Drift
Full-Scale Error
ZERR
ZDrift
FSE
After system zero-scale calibration
After system full-scale calibration
(Notes 4 and 5)
1 µV
50 nV/°C
2 ppmFSR
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Maxim Integrated 2



Maxim Integrated MAX11259
MAX11259
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
Electrical Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V to 3.6V, VREFP - VREFN = VAVDD, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)(Note 3)
PARAMETER
Full-Scale Error Drift
Common-Mode
Rejection
SYMBOL
FSEDrift
CMR
CONDITIONS
DC rejection
50Hz/60Hz rejection (Note 6)
DC rejection with PGA gain 64
MIN TYP MAX UNITS
0.05
ppmFSR/°C
110 130
110 130
80 105
dB
AVDD, AVSS Supply
Rejection Ratio
DVDD Supply Rejection
Ratio
PSRRA
PSRRD
DC rejection with PGA gain 128
DC rejection
50Hz/60Hz rejection (Note 6)
DC rejection with PGA gain 128
DC rejection
50Hz/60Hz rejection (Note 6)
DC rejection with PGA gain 128
95
73 95
75 95
65 75
105 115
105 115
90 110
dB
dB
PGA
Gain Setting
Noise-Spectral Density
NSD
Low-noise mode
Low-power mode
Gain = 1
1 128 V/V
6.2
nV/√Hz
10
0.75
Gain Error, Not
Calibrated
GERR
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
1.2
2
3
%
4.5
6
Gain = 64
Gain = 128
5.5
2
Output Voltage Range
VOUTRNG
VAVSS
+ 0.3
VAVDD
- 0.3
V
MUX
Channel-to-Channel
Isolation
ISOCH-CH DC
140 dB
GENERAL-PURPOSE OUTPUTS
Resistance (On)
RON
GPO_ output current = 30mA,
GPOGND connected to AVSS
3.5 10
Maximum Current (On)
IMAX
Per output
Total from all outputs into GPOGND
bump (Note 6)
30
90
mA
mA
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