Document
HX8801 Data Sheet TFT-LCD AV CONTROLLER
Version 02 August, 2002
Himax Technologies, Inc.
1F, No.12, Nanke 8th Road, Tainan Science-Based Industrial Park, Tainan County, Taiwan 741, R.O.C.
TEL: 886-6-505-0880 FAX: 886-6-505-0891
DOC No:HX8801-17
HX8801
TFT-LCD AV CONTROLLER
August 2002, Version 02
1. General Description
The HX8801 is a timing controller for small panel TFT-LCD. It provides horizontal and vertical control timing to TFT-LCD source and gate drivers. Built-in vertical synchronization detection generates vertical synchronization signal internally without the extra components. Built-in phase lock loop sub-function with external VCO and low pass filter circuits produces system clock which synchronizes input composite synchronization signal.
2. Features
Support six display resolution mode, up to 1440 × 234. Master clock frequency: 30 MHz max. Built-in vertical sync. detection to omit the external sync. separator. Single supply voltage: +5.0V. Shift clock signals for the source driver (3-φ Clock). Line inversion driving scheme. Support NTSC/PAL TV system. Provides source and gate drivers control timing. Provides flip and mirror scan control. 48 pins LQFP.
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Technologies, Inc.
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3. Block Diagram
HX8801 TFT-LCD AV CONTROLLER
HX8801
NPC
Composite Sync.
CVS
Processing
Sync. Separator
VS
EXT_VS
NPC
Vertical Sync. Processing
L.P.F. PLL
Mode Detection
V.C.O.
VCO_CLK_OUT
Source Driver Control
DHS, CPH1~3 OEV CKV OEH STHL(R) LRC
RSC1~3
Gate Driver Control
DVS
STVU(D) Q1H VCOM UDC
EXT_NPC NPC
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Technologies, Inc.
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4. Pin Assignment
HX8801 TFT-LCD AV CONTROLLER
VCO_CLK_OUT 25 VCO_CLK_IN 26 DVS 27 N.C. 28 HWRESETZ 29 VS 30 UDC_INV 31 GND 32 RSC2 33 DHS 34 CVS 35 GND 36
UDC 37 N.C. 38 LRC 39 LRC_INV 40 N.C. 41 EXT_VS 42 NPC 43 VCOM 44 EXT_NPC 45 HS_REF_FBO 46 HS_REF_FBI 47 VCC 48
HX8801
(48-pin LQFP)
24 VCC 23 GND 22 RSC1 21 PH2 20 PH1 19 CPH3 18 CPH2 17 CPH1 16 CKV 15 PDO 14 STHR 13 STHL
12 VCC 11 STVU 10 STVD 9 RSC3 8 Q1H 7 GND 6 N.C. 5 N.C. 4 OEV 3 OEH 2 INV_IN 1 INV_OUT
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Technologies, Inc.
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5. Pin Description
HX8801 TFT-LCD AV CONTROLLER
Pin no. Symbol 1 INV_OUT
I/O Description O Inverter output
2
INV_IN
I Inverter input
3
OEH
O Source driver output enable control signal
4
OEV
O Gate driver output enable control signal
5 N.C.(1)
6 N.C. (1)
7 GND
Ground
8
Q1H
O
R, G, B video signal sample & hold multiplexer control signal for source driver
9
RSC3(2)
I Resolution mode setting pin III
Start pulse for gate driver.
10
STVD
O (1) STVD is “HiZ”, when UDC=”L”
(2) STVD is ”Output”, when UDC=”H”
Start pulse for gate driver.
11
STVU
O (1) STVU is ”HiZ”, when UDC=”H”
(2) STVU is ”Output”, when UDC=”L”
12 VCC
+5.0V for controller power
Start pulse for source driver. 13 STHL O (1) STHL is ”HiZ”, when LRC=”H”
(2) STHL is ”Output”, when LRC=”L”
Start pulse for source driver. 14 STHR O (1) STHR is ”HiZ”, when LRC=”L”
(2) STHR is ”Output”, when LRC=”H”
15 PDO O Phase detector output
16 CKV O Shift clock for gate driver
17 CPH1 O Shift clock φ1 for source driver 18 CPH2 O Shift clock φ2 for source driver 19 CPH3 O Shift clock φ3 for source driver 20 PH1(3) I Phase compensation setting pin I 21 PH2(3) I Phase compensation setting pin II 22 RSC1(2) I Resolution mode setting pin I
23 GND
Ground
24 VCC
+5.0V for controller power
25 VCO_CLK_OUT O Inverted system clock signal output
System clock input. It connects with external VCO
26
VCO_CLK_IN
I
and low pass filter circuits to generate system clock which synchronizes input composite
synchronization signal
27
DVS
O
Negative polarity vertical synchronization signal output
28 N.C. (1)
29 HWRESETZ(4) I Active low global reset signal input
30
VS
I
Negative polarity vertical synchronization signal input which is from the external synchronization
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HX8801 TFT-LCD AV CONTROLLER
Pin no. Symbol
I/O
Description
separator circuits
31
UDC_INV
O UDC inverted signal output
32 GND
Ground
33 RSC2(2) I Resolution mode setting pin II
34
DHS
O
Horizontal synchronization signal output with negative polarity
35
CVS
I
Composite synchronization signal input with positive polarity
36 GND
Ground
Up / Down scan setting pin
37 UDC I (1) Normal scan, when UDC=”L”
38 N.C. (1)
(2) Reverse scan, when UDC=”H”
Left / Right scan setting pin
39 LRC I (1) Normal scan, LRC=”L”
(2) Reverse scan, LRC=”H”
40 LRC_INV O LRC inverted signal output 41 N.C. (1)
VS detection setting pin
(1) VS is from external detection , when
42 EXT_VS I EXT_VS=”H”
(2) VS is from internal detection , when
EXT_VS=”L”
43 Video signal input format setting pin
NPC
I/O (1) Input format is ”PAL”, when NPC=”L”
(2) Input format is ”NTSC, when NPC=”H”
44
VCOM
O
Toggling signal for common electrode generation circuits
NPC I/O setting pin
45 EXT_NPC I (1) NPC is “Output”, when EXT_NPC =”L”
(2) NPC is “Input”, when EXT_NPC =”H”
46
.