SDRAM Memory. HY57V561620FT-5 Datasheet

HY57V561620FT-5 Memory. Datasheet pdf. Equivalent

HY57V561620FT-5 Datasheet
Recommendation HY57V561620FT-5 Datasheet
Part HY57V561620FT-5
Description 256M (16M x 16bit) Hynix SDRAM Memory
Feature HY57V561620FT-5; 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell A.
Manufacture Hynix Semiconductor
Datasheet
Download HY57V561620FT-5 Datasheet




Hynix Semiconductor HY57V561620FT-5
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Dec. 2009
1



Hynix Semiconductor HY57V561620FT-5
111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
Document Title
256Mbit (16M x16) Synchronous DRAM
Revision History
Revision No.
0.1
0.2
0.3
History
Initial Draft
Define :
Current value (Page 11 ~ 12)
1. Cerrect :
1-1. 4Banks x 2Mbits x32 --> 4Banks x 4Mbits x16(Ordering in-
formation; Page 06).
1-2. VDDQ / VSSQ : Power supply for output buffers (Page 08).
2. Remove :
Special Power consumption function of Auto TCSR(Temperature
Compensated Self Refresh) and PASR(Partial Array Self Refresh).
3. Define :
AC Operating TEST condition and AC / DC Output Load circuit
(page 10 & 11).
Before :
Draft Date
Dec. 2005
Apr. 2006
Jun. 2006
Remark
Preliminary
Preliminary
Preliminary
Output
Vtt=1.4V
RT=500
30pF
Output
Z0 = 50
Vtt=1.4V
RT=50
30pF
DC Output Load Circuit
AC Output Load Circuit
Rev 1.2 / Dec. 2009
2



Hynix Semiconductor HY57V561620FT-5
Revision No.
After :
History
0.3
Output
VTT =
1.4V
RT = 50
Ohom
50pF
Output
DC Output Load Circuit
Z0 = 50 Ohom
VTT =
1.4V
RT = 50
Ohom
50pF
AC Output Load Circuit
4. Specification change :
4-1. IOH / IOL (Page 11)
Before : -2 / 2mA --> After : -4 / 4mA.
4-2. tDH, tAH, tCKH, tCH (Page 13)
Before : 1.0ns --> After : 0.8ns.
1. Delete
1-1. COMMAND TRUTH TABLE for Extended Mode Register
(Page15)
2. Insert
2-1. DQM TRUTH TABLE (Page16)
0.4 3. Specitication change :
3-1. IDD6
Before : 3 / 1.5mA --> After : 2 / 1mA
3-2. IDD3N
Before :25mA --> After : 30mA
3-3. tCHW / tCLW Change [HY57V561620F(L)T(P)-6x]
Before :2.0ns --> After : 2.5ns
1.0 Final Ver.
1. Update
1-1. Ordering Information table (Page 5)
200Mhz products added
1-2. DC Characteristics II (Page 11)
200Mhz spec. added
1-3. AC Characteristics I (Page 12)
1.1 200Mhz spec. added
1-4 AC Characteristics II (Page 13)
200Mhz spec. added
2. Cerrect
HY57V561620FT-6 --> HY57V561620FLT-6
(Ordering Information. Page 5)
1.2
Revise (Command Truth Table / P.15)
Burst Read Single Write : /WE H --> L
Draft Date
Jun. 2006
Jun. 2006
Sep. 2006
Apr. 2008
Dec. 2009
Remark
Preliminary
Preliminary
Final
Final
Final







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