256M (16M x 16bit) Hynix SDRAM Memory
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as ...
Description
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
256M (16Mx16bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as 4banks of 4,194,304 x 16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Dec. 2009
1
111
Synchronous DRAM Memory 256Mbit HY57V561620F(L)T(P) Series
Document Title
256Mbit (16M x16) Synchronous DRAM
Revision History
Revision No. 0.1 0.2
0.3
History
Initial Draft
Define : Current value (Page 11 ~ 12)
1. Cerrect : 1-1. 4Banks x 2Mbits x32 --> 4Banks x 4Mbits x16(Ordering information; Page 06).
1-2. VDDQ / VSSQ : Power supply for output buffers (Page 08).
2. Remove : Special Power consumption function of Auto TCSR(Temperature Compensated Self Refresh) and PASR(Partial Array Self Refresh).
3. Define : AC Operating TEST condition and AC / DC Output Load circuit (page 10 & 11).
Before :
Draft Date Dec. 2005 Apr. 2006
Jun. 2006
Remark Preliminary Preliminary
Preliminary
Output
Vtt=1.4V RT=500 Ω
30pF
Output
Z0 = 50Ω
Vtt=1.4V RT=50 Ω
30pF
DC Output Load Circuit
AC Output Load Circuit
Rev 1.2 / Dec. 2009
2
Revision No.
After :
History
0.3
Output
VTT = 1.4V
RT = 50 Ohom
50pF
Output
DC Output Load Circuit
Z0 = 50 Ohom
VTT = 1.4V
RT = 50 Ohom
50pF
AC Output Load Circuit
4. Specification change :
4-1. IOH / IOL (Page 11) Before : -2 / 2mA --> After : -4 / 4mA.
4-2. tDH, tAH, tCKH, tCH ...
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