N-CHANNEL MOSFET. uPA2560 Datasheet

uPA2560 MOSFET. Datasheet pdf. Equivalent

uPA2560 Datasheet
Recommendation uPA2560 Datasheet
Part uPA2560
Description Dual N-CHANNEL MOSFET
Feature uPA2560; DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2560 Dual N-CHANNEL MOSFET FOR SWITCHING DESCRIPTION Th.
Manufacture Renesas
Datasheet
Download uPA2560 Datasheet




Renesas uPA2560
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2560
Dual N-CHANNEL MOSFET
FOR SWITCHING
DESCRIPTION
The μ PA2560 is Dual N-channel MOSFETs designed for Back light
inverters and power management applications of portable equipments.
Dual N-channel MOSFETs are assembled in one package, to
contribute minimize the equipments.
FEATURES
4.5 V drive available
Low on-state resistance
RDS(on)1 = 50 mΩ MAX. (VGS = 10 V, ID = 2 A)
RDS(on)2 = 83 mΩ MAX. (VGS = 4.5 V, ID = 2 A)
Built-in gate protection diode
Small and surface mount package (8-pin VSOF (2429))
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
30 V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20 V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit, 5 s) Note2
Total Power Dissipation (2 units, 5 s) Note2
ID(DC)
ID(pulse)
PT1
PT2
±4.5 A
±18 A
1.5 W
2.2 W
Channel Temperature
Tch 150 °C
Storage Temperature
Tstg 55 to +150 °C
Notes 1. PW 10 μs, Duty Cycle 1%
2. Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mm.
PACKAGE DRAWING (Unit: mm)
2.9±0.1
0.65
8
5
A
0.17±0.05
0 to 0.025
1
0.32±0.05
4
0.05 M S A
S
1: Source1
2: Gate1
3: Source2
4: Gate2
5, 6: Drain2
7, 8: Drain1
EQUIVALENT CIRCUIT (1/2)
Drain
ORDERING INFORMATION
PART NUMBER
μ PA2560T1H-T1-AT Note
μ PA2560T1H-T2-AT Note
LEAD PLATING
PACKING
PACKAGE
Pure Sn
8 mm embossed taping
8-pin VSOF (2429)
3000 p/reel
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
Gate
Body
Diode
Gate
Protection
Diode
Source
Marking: 2560
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
Caution This product is electrostatic-sensitive device due to low ESD capability and should be handled with
caution for electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19947EJ1V0DS00 (1st edition)
Date Published September 2009 NS
Printed in Japan
2009



Renesas uPA2560
μ PA2560
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Body Diode Forward Voltage Note
Note Pulsed
SYMBOL
TEST CONDITIONS
IDSS VDS = 30 V, VGS = 0 V
IGSS VGS = ±16 V, VDS = 0 V
VGS(off)
VDS = 10 V, ID = 1 mA
| yfs |
VDS = 10 V, ID = 2 A
RDS(on)1
VGS = 10 V, ID = 2 A
RDS(on)2
VGS = 4.5 V, ID = 2 A
Ciss VDS = 10 V,
Coss
VGS = 0 V,
Crss f = 1.0 MHz
td(on)
VDD = 15 V, ID = 2 A,
tr VGS = 10 V,
td(off)
tf
RG = 6 Ω
QG VDD = 24 V, VGS = 10 V,
ID = 4.5 A
VF(S-D)
IF = 4.5 A, VGS = 0 V
MIN.
1.0
1
TYP.
38
48
310
65
27
6
2.8
15
2.4
6.6
0.9
MAX.
1
±10
2.5
50
83
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
V
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VGS 90%
ID 90%
ID
Wave Form
0 10%
td(on)
ID
tr td(off)
90%
10%
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet G19947EJ1V0DS



Renesas uPA2560
μ PA2560
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
10 R
D
S(on)
(VG
Lim1
S=4
it ed
.5 V
)
ID(DC)
1
ID(pulse)
300
μs
11
0
110
0m
1
m
1
s
s
11ms
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.5
Mounted on FR-4 board of
25.4 mm x 25.4 mm x 0.8 mm
2
1.5
2 units
1
1 unit
0.5
0
0 25 50 75 100 125 150 175
TA - Ambient Temperature - °C
0.1
0.01
Single pulse
Mounted on FR-4 board of
25.4 mm × 25.4 mm × 0.8 mm
0.1 1
10
VDS - Drain to Source Voltage - V
100
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
10
1
1m
10 m
Single pulse
Mounted on FR-4 board of 25.4 mm × 25.4 mm × 0.8 mm
100 m
1
10
PW - Pulse Width - s
100 1000
Data Sheet G19947EJ1V0DS
3







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