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P-CHANNEL MOSFET. uPA2590 Datasheet

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P-CHANNEL MOSFET. uPA2590 Datasheet







uPA2590 MOSFET. Datasheet pdf. Equivalent




uPA2590 MOSFET. Datasheet pdf. Equivalent





Part

uPA2590

Description

N- AND P-CHANNEL MOSFET

Manufacture

Renesas

Datasheet
Download uPA2590 Datasheet


Renesas uPA2590

uPA2590; .


Renesas uPA2590

.


Renesas uPA2590

.



Part

uPA2590

Description

N- AND P-CHANNEL MOSFET

Manufacture

Renesas

Datasheet
Download uPA2590 Datasheet




 uPA2590
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2590
N- AND P-CHANNEL MOSFET
FOR SWITCHING
DESCRIPTION
The μ PA2590 is N- and P-channel MOSFETs designed for
DC/DC converters and power management applications of
portable equipments.
N- and P-channel MOSFETs are assembled in one package, to
contribute minimize the equipments.
PACKAGE DRAWING (Unit: mm)
2.9±0.1
0.65
8
5
A
0.17±0.05
0 to 0.025
FEATURES
4.5 V drive available
Low on-state resistance
N-channel RDS(on)1 = 50 mΩ MAX. (VGS = 10 V, ID = 2 A)
RDS(on)2 = 83 mΩ MAX. (VGS = 4.5 V, ID = 2 A)
P-channel RDS(on)1 = 72 mΩ MAX. (VGS = 10 V, ID = 2 A)
RDS(on)2 = 105 mΩ MAX. (VGS = 4.5 V, ID = 2 A)
Built-in gate protection diode
Small and surface mount package (8-pin VSOF (2429))
1
0.32±0.05
S
4
0.05 M S A
N-channel 1: Source
2: Gate
7, 8: Drain
P-channel 3: Source
4: Gate
5, 6: Drain
ORDERING INFORMATION
PART NUMBER
μ PA2590T1H-T1-AT Note
μ PA2590T1H-T2-AT Note
LEAD PLATING
Pure Sn
PACKING
8 mm embossed taping
3000 p/reel
PACKAGE
8-pin VSOF (2429)
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
Marking: 2590
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19217EJ1V0DS00 (1st edition)
Date Published May 2008 NS
Printed in Japan
2008





 uPA2590
μ PA2590
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
Drain to Source Voltage (VGS = 0 V)
VDSS
30 30
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit, 5 s) Note2
Total Power Dissipation (2 units, 5 s) Note2
VGSS
ID(DC)
ID(pulse)
PT1
PT2
±20
±4.5
±18
1.5
1.24
m20
m4.5
m18
Channel Temperature
Tch
150
Storage Temperature
Tstg
55 to +150
Notes 1. PW 10 μs, Duty Cycle 1%
2. Mounted on FR-4 board of 25.4 mm x 25.4 mm x 0.8 mmt
UNIT
V
V
A
A
W
W
°C
°C
EQUIVALENT CIRCUIT
N-channel
Drain
P-channel
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Gate
Body
Diode
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
Caution This product is electrostatic-sensitive device due to low ESD capability and should be handled with
caution for electrostatic discharge.
2 Data Sheet G19217EJ1V0DS





 uPA2590
μ PA2590
ELECTRICAL CHARACTERISTICS (TA = 25°C)
N-channel MOSFET
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 30 V, VGS = 0 V
Gate Leakage Current
IGSS VGS = ±16 V, VDS = 0 V
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(off)
| yfs |
RDS(on)1
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 2 A
VGS = 10 V, ID = 2 A
RDS(on)2
VGS = 4.5 V, ID = 2 A
Input Capacitance
Ciss VDS = 10 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1.0 MHz
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 2 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 6 Ω
Fall Time
tf
Total Gate Charge
QG VDD = 24 V, VGS = 10 V,
Body Diode Forward Voltage Note
VF(S-D)
ID = 4.5 A
IF = 4.5 A, VGS = 0 V
Note Pulsed
MIN.
1.0
1
TYP.
38
48
310
65
27
6
2.8
15
2.4
6.6
0.9
MAX.
1
±10
2.5
50
83
UNIT
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
V
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VGS 90%
ID 90%
ID
Wave Form
0 10%
td(on)
ID
tr td(off)
90%
10%
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
Data Sheet G19217EJ1V0DS
3



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