MOS FET. uPA2791GR Datasheet

uPA2791GR FET. Datasheet pdf. Equivalent

uPA2791GR Datasheet
Recommendation uPA2791GR Datasheet
Part uPA2791GR
Description SWITCHING N- AND P-CHANNEL POWER MOS FET
Feature uPA2791GR; DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2791GR SWITCHING N- AND P-CHANNEL POWER MOS FET DESCRIPT.
Manufacture Renesas
Datasheet
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Renesas uPA2791GR
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA2791GR
SWITCHING
N- AND P-CHANNEL POWER MOS FET
DESCRIPTION
The μ PA2791GR is N- and P-channel MOS Field Effect
Transistors designed for switching application.
FEATURES
Low on-state resistance
N-channel RDS(on)1 = 36.0 mΩ MAX. (VGS = 10 V, ID = 3.0 A)
RDS(on)2 = 50.0 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A)
P-channel RDS(on)1 = 82 mΩ MAX. (VGS = 10 V, ID = 3.0 A)
RDS(on)2 = 110 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A)
Low gate charge
N-channel QG = 10 nC TYP. (VGS = 10 V)
P-channel QG = 8.3 nC TYP. (VGS = 10 V)
Built-in gate protection diode
Small and surface mount package (Power SOP8)
PACKAGE DRAWING (Unit: mm)
85
N-channel 1 : Source 1
2 : Gate 1
7, 8 : Drain 1
P-channel 3 : Source 2
4 : Gate 2
5, 6 : Drain 2
14
5.37 MAX.
6.0 ± 0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ± 0.2
0.10
ORDERING INFORMATION
PART NUMBER
μ PA2791GR-E1-AT Note
μ PA2791GR-E2-AT Note
LEAD PLATING
Pure Sn
PACKING
Tape 2500
p/reel
PACKAGE
Power SOP8
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
EQUIVALENT CIRCUIT
N-channel
Drain
P-channel
Drain
Gate
Body
Diode
Gate
Body
Diode
Gate
Protection
Diode
Source
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
Caution This product is electrostatic-sensitive device due to low ESD capability and should be handled with
caution for electrostatic discharge. VESD ± 600 V TYP. (C = 100 pF, R = 1.5 kΩ)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G18207EJ2V0DS00 (2nd edition)
Date Published November 2007 NS
2006, 2007
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.



Renesas uPA2791GR
μ PA2791GR
ABSOLUTE MAXIMUM RATINGS (TA = 25°C. All terminals are connected.)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
Drain to Source Voltage (VGS = 0 V)
VDSS
30
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C) Note2
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 units) Note2
VGSS
ID(DC)
ID(pulse)
PT1
PT2
±20
±5
±20
1.7
2.0
Channel Temperature
Tch
150
Storage Temperature
<R> Single Avalanche Current Note3
<R> Single Avalanche Energy Note3
Tstg
IAS
EAS
55 to +150
5
2.5
Notes 1. PW 10 μs, Duty Cycle 1%
2. Mounted on ceramic substrate of 2000 mm2 x 1.6 mmt
<R>
3. Starting Tch = 25°C, VDD = 1/2 x VDSS, RG = 25 Ω, L = 100 μH, VGS = VGSS 0 V
30
m20
m5
m20
5
UNIT
V
V
A
A
W
W
°C
°C
A
mJ
2 Data Sheet G18207EJ2V0DS



Renesas uPA2791GR
μ PA2791GR
ELECTRICAL CHARACTERISTICS (TA = 25°C. All terminals are connected.)
N-channel
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current
IDSS VDS = 30 V, VGS = 0 V
10 μA
Gate Leakage Current
IGSS VGS = ±16 V, VDS = 0 V
±10 μA
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(off)
| yfs |
RDS(on)1
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 3 A
VGS = 10 V, ID = 3.0 A
1.0 2.5 V
2.0 S
28.5 36.0 mΩ
RDS(on)2
VGS = 4.5 V, ID = 3.0 A
36.0 50.0 mΩ
Input Capacitance
Ciss VDS = 10 V,
400 pF
Output Capacitance
Coss
VGS = 0 V,
80 pF
Reverse Transfer Capacitance
Crss f = 1 MHz
50 pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 3 A,
7 ns
Rise Time
tr VGS = 10 V,
4 ns
Turn-off Delay Time
td(off)
RG = 10 Ω
21 ns
Fall Time
tf
5 ns
Total Gate Charge
QG ID = 5 A,
10 nC
Gate to Source Charge
QGS VDD = 24 V,
1.5 nC
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
VGS = 10 V
IF = 5 A, VGS = 0 V
2.7
0.86
nC
V
Reverse Recovery Time
trr IF = 5 A, VGS = 0 V,
20 ns
Reverse Recovery Charge
Qrr di/dt = 50 A/μs
16 nC
Note Pulsed
<R> TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
ID
VDD
IAS
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
90%
VGS
90%
10% 10%
tr td(off)
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
Data Sheet G18207EJ2V0DS
3







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