IXFR50N50

HiPerFETTM Power MOSFETs ISOPLUS247TM (Electrically Isolated Back Surface) Single Die MOSFET IXFR 50N50 IXFR 55N50 VDSS ID25 500 V 43 A 500 V 48 A trr ≤ 250 ns RDS(on) 100 mΩ 90 mΩ Symbol VDSS V DGR VGS V GSM ID25 IDM IAR EAR EAS dv/dt PD TJ TJM Tstg TL VISOL Weight Symbol VDSS VGS(th) I GSS IDSS RDS(on) Test Conditions Maximum Ratings TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MΩ Continuous Transient TC = 25°C TC = 25°C, Pulse width limited by TJM TC = 25°C TC = 25°C TC = 25°C IS ≤ IDM, di/dt ≤ 100 A/µs, VDD ≤ VDSS TJ ≤ 150°C, RG = 2 Ω TC = 25°C 1.6 mm (0.063 in.) from case for 10 s 50/60 Hz, RMS t = 1 min 50N50 55N50 50N50 55N50 50N50 55N50 500 500 ±20 ±30 43 48 200 220 50 55 60 3 5 400 -40 ... +150 150 -40 ... +150 300 2500 5 V V V V A A A A A A mJ J V/ns W °C °C °C °C V~ g Test Conditions VGS = 0 V, ID = 1mA VDS = VGS, ID = 8mA VGS = ±20 V, VDS = 0 VDS = VDSS VGS = 0 V VGS = 10 V, ID = IT Note 1 Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 500 V 2.5 4.5 V ±200 nA TJ = 25°C TJ = 125°C 50N50 55N50 25 µA 2 mA 100 mΩ 90 mΩ ISOPLUS 247TM G D Isolated back surface* G = Gate S = Source D = Drain * Patent pending Features l Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation l Low drain to tab capacitance(<50pF) l Low RDS (on) HDMOSTM process l Rugged polysilicon gate cell structure l Unclamped Inductive Switching (UIS) rated l Fast intrinsic Rec...