PSD813F1A

PSD813F1A Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V NOT FOR NEW DESIGN FEATURES SUMMARY ■ DUAL BANK FLASH MEMORIES Figure 1. Packages – 1 Mbit of Primary Flash Memory (8 Uniform Sectors) )– 256 Kbit Secondary EEPROM (4 Uniform t(sSectors) – Concurrent operation: read from one ucmemory while erasing and writing the dother ro )■ 16 Kbit SRAM P t(s■ PLD WITH MACROCELLS te c– Over 3,000 Gates Of PLD: DPLD and le uCPLD d– DPLD - User-defined Internal chip-select so rodecoding b P– CPLD with 16 Output Macrocells (OMCs) - O teand 24 Input Macrocells (IMCs) ■ 27 RECONFIGURABLE I/Os ) le– 27 individually configurable I/O port pins t(s sothat can be used for the following c bfunctions (16 I/O ports configurable as uopen-drain outputs): d - OMCU I/Os ro )PLD I/Os P t(sLatched MCU address output; and te cSpecial function I/Os le u■ ENHANCED JTAG SERIAL PORT so rod– Built-in JTAG-compliant serial port allows full-chip In-System Programmability (ISP) b P– Efficient manufacturing allows for easy O teproduct testing and programming le■ PAGE REGISTER o– Internal page register that can be used to s expand the microcontroller address space b by a factor of 256. O■ PROGRAMMABLE POWER MANAGEMENT PQFP52 (M) PLCC52 (J) TQFQ64 (U) ■ HIGH ENDURANCE: – 100,000 Erase/WRITE Cycles of Flash Memory – 10,000 Erase/WRITE Cycles of EEPROM – 1,000 Erase/WRITE Cycles of PLD – Data Retention: 15-year minimum at 90°C (for Main Flash, Boot, PLD and Configuration bits). ■ SINGLE SUPP...