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MM74HC4543 Dataheets PDF



Part Number MM74HC4543
Manufacturers National Semiconductor
Logo National Semiconductor
Description BCD-to-7 Segment Latch/Decoder/Driver
Datasheet MM74HC4543 DatasheetMM74HC4543 Datasheet (PDF)

MM54HC4543 MM74HC4543 BCD-to-7 Segment Latch Decoder Driver for Liquid Crystal Displays January 1988 MM54HC4543 MM74HC4543 BCD-to-7 Segment Latch Decoder Driver for Liquid Crystal Displays General Description The MM54HC4543 MM74HC4543 BCD-to-7 segment latch decoder driver utilize advanced silicon-gate CMOS technology and can be used either as a high speed decoder or as a display driver This circuit contains a 4-bit latch BCD-to-7 segment decoder and 7 output drivers Data on the input pins flo.

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MM54HC4543 MM74HC4543 BCD-to-7 Segment Latch Decoder Driver for Liquid Crystal Displays January 1988 MM54HC4543 MM74HC4543 BCD-to-7 Segment Latch Decoder Driver for Liquid Crystal Displays General Description The MM54HC4543 MM74HC4543 BCD-to-7 segment latch decoder driver utilize advanced silicon-gate CMOS technology and can be used either as a high speed decoder or as a display driver This circuit contains a 4-bit latch BCD-to-7 segment decoder and 7 output drivers Data on the input pins flow through to the output when the LATCH ENABLE (LE) is high and is latched on the high to low transition of the LE input The PHASE input (PH) controls the polarity of the 7 segment outputs When PH is low the outputs are true 7 segment and when PH is high the outputs are inverted 7 segment When the PHASE input is driven by a liquid crystal display (LCD) backplane waveform the segment pins output the correct segment waveform for proper LCD AC drive voltages In addition a BLANKING INPUT (Bl) is provided which will blank the display The MM54HC4543 MM74HC4543 are functionally and pinout equivalent to the CD4543BC CD4543BM and the MC14543BA MC14543BC All inputs are protected from damage due to static discharge by diodes to VCC and ground Features Y Typical propagation delay 60 ns Y Supply voltage range 2 – 6V Y Maximum input current 1 mA Y Maximum quiescent supply current 80 mA (74HC) Y Display blanking Y Low dynamic power consumption Connection Diagram Dual-In-Line Package Top View TL F 5128 – 1 Order Number MM54HC4543 or MM74HC4543 Display Format TL F 5128 – 2 Truth Table Inputs Outputs LE Bl Ph D C B A a b c d e f g Display X H L X X X X L L L L L L L Blank H L L L L L LHHHHHHL H L L L L LHLHHL L L L H L L L LHLHHLHHLH H L L L LHHHHHHL LH 0 1 2 3 H L L LHL L LHHL LHH H L L LHLHHLHHLHH H L L LHHLHLHHHHH H L L LHHHHHHL L L L 4 5 6 7 HL HL HL HL L HL L LHHHHHHH 8 L HL LHHHHHLHH 9 L H L H L L L L L L L L Blank L H L H H L L L L L L L Blank HL HL HL HL L H H L L L L L L L L L Blank L H H L H L L L L L L L Blank L H H H L L L L L L L L Blank L H H H H L L L L L L L Blank L L L XXXX Inverse of Output Display H Combinations as Above above X don’t care esame as above combinations efor liquid crystal readouts apply a square wave to Ph edepends upon the BCD code previously applied when LE H C1995 National Semiconductor Corporation TL F 5128 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S O Package only b0 5 to a7 0V b1 5 to VCCa1 5V b0 5 to VCCa0 5V g20 mA g25 mA g50 mA b65 C to a150 C 600 mW 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Min 2 0 b40 b55 Input Rise or Fall Times (tr tf) VCCe2 0V VCCe4 5V VCCe6 0V Max 6 VCC a85 a125 1000 500 400 Units V V C C ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TAe25 C Typ 74HC 54HC TAeb40 to 85 C TAeb55 to 125 C Guaranteed Limits Units VIH Minimum High Level Input Voltage 2 0V 4 5V 6 0V 15 15 3 15 3 15 42 42 15 V 3 15 V 42 V VIL Maximum Low Level Input Voltage 2 0V 4 5V 6 0V 05 05 1 35 1 35 18 18 05 V 1 35 V 18 V VOH Minimum High Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2 0V 2 0 1 9 4 5V 4 5 4 4 6 0V 6 0 5 9 19 44 59 19 V 44 V 59 V VINeVIH or VIL lIOUTls0 4 mA lIOUTls0 52 mA 4 5V 4 2 3 98 6 0V 5 7 5 48 VOL Maximum Low Level VINeVIH or VIL Output Voltage lIOUTls20 mA 2 0V 0 0 1 4 5V 0 0 1 6 0V 0 0 1 3 84 5 34 01 01 01 37 V 52 V 01 V 01 V 01 V VINeVIH or VIL lIOUTls0 4 mA lIOUTls0 52 mA 4 5V 0 2 0 26 6 0V 0 2 0 26 IIN Maximum Input VINeVCC or GND 6 0V Current g0 1 0 33 0 33 g1 0 04 04 g1 0 V V mA ICC Maximum Quiescent VINeVCC or GND 6 0V 8 0 80 Supply Current IOUTe0 mA 160 mA Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL speci.


MM54HC4543 MM74HC4543 DS8669


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