Document
PH4025L
N-channel TrenchMOS logic level FET
Rev. 01 — 22 August 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
1.2 Features
I Logic level threshold I Optimized for use in DC-to-DC
converters I 100 % RG tested
1.3 Applications
I DC-to-DC converters I Voltage regulators
I Lead-free package I Very low switching and conduction
losses I 100 % ruggedness tested
I Switched-mode power supplies I PC Motherboards
1.4 Quick reference data
I VDS ≤ 25 V I RDSon ≤ 4.0 mΩ
I ID ≤ 99 A I QGD = 5 nC (typ)
2. Pinning information
Table 1. Pinning Pin Description 1, 2, 3 source (S) 4 gate (G) mb mounting base; connected to drain (D)
Simplified outline
mb
1234
SOT669 (LFPAK)
Symbol
D
G mbb076 S
NXP Semiconductors
PH4025L
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information
Type number
Package
Name
PH4025L
LFPAK
Description plastic single-ended surface-mounted package (lfpak); 4 leads
4. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS VDGR VGS ID
drain-source voltage drain-gate voltage (DC) gate-source voltage drain current
IDM peak drain current Ptot total power dissipation Tstg storage temperature Tj junction temperature Source-drain diode
25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 °C; VGS = 10 V; see Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 Tmb = 25 °C; see Figure 1
IS source current ISM peak source current Avalanche ruggedness
Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs
EDS(AL)S non-repetitive drain-source avalanche energy
unclamped inductive load; ID = 56 A; tp = 0.16 ms; VDS ≤ 25 V; RGS = 50 Ω; VGS = 10 V; starting at Tj = 25 °C
Min −55 −55
-
-
Version SOT669
Max 25 25 ±20 99 67.5 300 46.4 +150 +150
Unit V V V A A A W °C °C
52 A 208 A
150 mJ
PH4025L_1
Product data sheet
Rev. 01 — 22 August 2007
© NXP B.V. 2007. All rights reserved.
2 of 12
NXP Semiconductors
120
Pder (%)
80
003aab937
PH4025L
N-channel TrenchMOS logic level FET
120
Ider (%)
80
003aab555
40 40
0 0 50 100 150 200 Tmb (°C)
Pder = P----t--o--P-t-(--t2-o--5-t-°---C---) × 100 %
Fig 1. Normalized total power dissipation as a function of mounting base temperature
103
ID (A)
102
Limit RDSon = VDS/ ID
10
1
0 0 50 100 150 200 Tj (°C)
Ider = -I--D----(-I-2-D-5---°--C---) × 100 % Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab720
tp = 10 µs 100 µs
1 ms 10 ms DC 100 ms
10−1 10−1
1
10 102 VDS (V)
Tmb = 25 °C Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH4025L_1
Product data sheet
Rev. 01 — 22 August 2007
© NXP B.V. 2007. All rights reserved.
3 of 12
NXP Semiconductors
PH4025L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4. Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb) thermal resistance from junction to mounting base see Figure 4
Min Typ Max Unit - - 2 K/W
003aab721 10
Zth(j-mb) (K/W)
δ =0.5 1
0.2
10−1
0.1 0.05 0.02
P δ = tp T
single pulse
10−2 10−5
10−4
10−3
10−2
10−1
tp T
1 tp (s)
t 10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH4025L_1
Product data sheet
Rev. 01 — 22 August 2007
© NXP B.V. 2007. All rights reserved.
4 of 12
NXP Semiconductors
PH4025L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain leakage current
IGSS RG RDSon
gate leakage current
gate resistance
drain-source on-state resistance
Dynamic characteristics
ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C
ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 °C Tj = 150 °C Tj = −55 °C
VDS = 25 V; VGS = 0 V Tj = 25 °C Tj = 150 °C
VGS = ±16 V; VDS = 0 V f = 1 MHz
VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 °C Tj = 150 °C
VGS = 4.5 V; ID = 25 A; see Figure 6 and 8
QG(tot) QGS
total gate charge gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 11 and 12
QGS1 pre-VGS(th) gate-source charge
QGS2 post-VGS(th) gate-source charge
QGD
gate-drain charge
VGS(pl) gate-source plateau voltage
QG(tot) total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
Ciss input capacitance Coss output capacitance
VGS = 0 V; VDS =12 V; f = 1 MHz; see Figure 14
Crss reverse transfer capacitance
Ciss input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
td(on) tr
turn-on delay time rise time
VDS =12 V; RL = 0.5 Ω; VGS = 4.5 V; RG = 5.6 Ω
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain voltage trr reverse recovery time Qr recovered charge
IS =.