A67P0636A

A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. History 0.0 Initial issue Issue Date May 12, 2008 Remark Preliminary PRELIMINARY (May, 2008, Version 0.0) AMIC Technology, Corp. A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Features „ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) „ Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization „ Signal +2.5V ± 5% power supply „ Individual Byte Write control capability „ Clock enable ( CEN) pin to enable clock and suspend operations „ Clock-controlled and registered address, data and control signals „ Registered output for pipelined applications „ Three separate chip enables allow wide range of options for CE control, address pipelining „ Internally self-timed write cycle „ Selectable BURST mode (Linear or Interleaved) „ SLEEP mode (ZZ pin) provided „ Available in 100 pin LQFP package „ Industrial operating temperature range: -25°C to +85°C for -I series „ All Pb-free (Lead-free) products are RoHS compliant General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P1618A, A67P0636A SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for...