Document
NB3U1548C
3.3V/2.5V/1.8V/1.5V 160 MHz 1:4 LVCMOS/LVTTL Low Skew Over Voltage Tolerant Fanout Buffer
Description The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout
buffer targeted for clock generation in high performance telecommunication, networking and computing applications. The device is optimized for low skew clock distribution in low voltage applications. The input overvoltage tolerance enables using this device in mixed mode voltage applications. An output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output skew characteristics make the NB3U1548C ideal for those applications demanding well defined performance and repeatability. The NB3U1548C is packaged in a small SOIC−8 and in an TSSOP−8 package.
Features
• Low skew 1:4 Fanout Buffer • Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies • LVCMOS Input and Output Levels • 3.6 V Overvoltage Tolerance at the Clock and Control Inputs • Supports Clock Frequencies up to 160 MHz • LVCMOS Compatible Control Input for Output Disable • Output Disabled to a High Impedance State • −40°C to 85°C Ambient Operating Temperature • Available in Pb−Free RoHS Compliant Packages (SOIC−8,
TSSOP−8)
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
8 1
SOIC−8 D SUFFIX CASE 751
8
1 TSSOP−8 DT SUFFIX CASE 948S
MARKING DIAGRAMS 8
1548C ALYWG
G 1
8
154 YWW
AG
1
A = Assembly Location L = Wafer Lot Y = Year W, WW = Work Week G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 3
1
Publication Order Number: NB3U1548C/D
NB3U1548C
CLK_IN Q1 Q2 Q3
1 2 3 4
8 OE 7 VDD 6 GND 5 Q4
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTIONS
Number
Name
1 CLK_IN
2 Q1
3 Q2
4 Q3
5 Q4
6 GND
7 VDD
8 OE
Type
Input
Pulldown
Output
Output
Output
Output
Power
Power
Input
Pullup
Description Single−ended clock input. LVCMOS interface levels. Single−ended clock output. LVCMOS interface levels. Single−ended clock output. LVCMOS interface levels. Single−ended clock output. LVCMOS interface levels. Single−ended clock output. LVCMOS interface levels. Power supply ground. Power supply pin. Output enable pin. See Table 3. LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min Typ Max Units
CIN Input Capacitance
4 pF
CPD
Power Dissipation Capacitance
RPULLUP
Input Pullup Resistor
VDD = 3.465 V VDD = 2.375 V VDD = 1.95 V
VDD = 1.6 V
14 pF 13 pF 13 pF 12 pF 51 kW
RPULLDOWN
Input Pulldown Resistor
51 kW
ROUT
Output Impedance
VDD = 3.3 V ± 5% VDD = 2.5 V ± 5% VDD = 1.8 V ± 0.15 V VDD = 1.5 ± 0.1 V
9 10 12 15
W W W W
Function Table
Table 3. OE CONFIGURATION TABLE.