Document
NCP458R, NCP459
4 A Single Load Switch for Low Voltage Rail
The NCP458R and NCP459 are power load switch with very low Ron NMOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy.
Indeed, thanks to a best in class current consumption optimization with NMOS structure, leakage currents are drastically decreased. Offering optimized leakages isolation on the ICs connected on the battery.
Output discharge path is proposed, in the NCP459 version , to eliminate residual voltages on the external components connected on output pin.
Reverse voltage protection, from OUT to IN is offered in the NCP458R version.
Proposed in wide input voltage range from 0.75 V to 5.5 V, and a very small CSP8 1 x 2 mm2.
Features
• 0.75 V − 5.5 V Operating Range • 11 mW N−MOSFET • Vbias Rail Input • DC Current up to 4 A • Output Auto−Discharge Option • Reverse Blocking Option • Active High EN Pin • CSP8, 1 x 2 mm2, Pitch 0.5 mm
Typical Applications
• Notebooks • Tablets • Wireless • Mobile Phones • Digital Cameras
Vcc V+
SMPS
DCDC Converter
or
LDO
LS
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MARKING DIAGRAM
WLCSP8 CASE 567HD
XXXX AYWWG
A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package
PINOUT 12
A EN
GATE
B IN
OUT
C IN
OUT
D VBIAS
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of this data sheet.
NCP458−459
B1 C1 A2 D1
IN OUT IN OUT Gate EN Vbias GND
B2 C2 A1 D2
Platform IC’n
ENx EN
0
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 1
1
Publication Order Number: NCP458R/D
NCP458R, NCP459
DCDC Converter
or
LDO
LS
NCP458−459
B1 C1
IN
OUT
B2 C2
A2 D1
IN OUT Gate EN Vbias GND
A1 D2
Platform IC’n
ENx EN
0
Figure 2. Application Schematic with Vbias Connected to IN and No Gate Delay
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
EN A1
IN B1, C1
VBIAS
D1
GATE
A2
OUT
B2, C2
GND
D2
Type INPUT POWER POWER INPUT POWER POWER
Description Enable input, logic high turns on power switch . Load−switch input pin. External supply voltage input. OUT pin slew rate control (trise). Load−switch output pin. Ground connection.
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IN: B1, C1 GATE : A2 VBIAS : D1 IN: B1, C1 GATE : A2 VBIAS : D 1
NCP458R, NCP459
BLOCK DIAGRAMS
Control logic &
Charge Pump
Gate driver
Figure 3. NCP458R Block Diagram
Control logic &
Charge Pump
Gate driver
Figure 4. NCP459 Block Diagram
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OUT : B2, C 2
EN: A1 GND : D2
OUT : B2 , C 2 GND : D 2 EN : A1
NCP458R, NCP459
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
IN, OUT, EN, VBIAS, GATE Pins: (Note 1)
From IN to OUT Pins: Input/Output (Note 1) NCP459 From IN to OUT Pins: Input/Output (Note 1) NCP458R Human Body Model (HBM) ESD Rating are (Note 2)
VEN, VIN , VOUT, VBIAS, VGATE
VIN , VOUT
VIN , VOUT
ESD HBM
−0.3 to +6.5
0 to + 6.5 ±6.5 2000
V
V V V
Machine Model (MM) ESD Rating are (Note 2)
ESD MM
200 V
Latch−up protection.