Document
ESD7102, SZESD7102
ESD Protection Diodes
Low Capacitance ESD Protection Diodes for High Speed Data Line
The ESD7102 transient voltage suppressor is designed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The small form factor, flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0 and HDMI.
Features
• Low Capacitance (0.3 pF Typical, I/O to GND) • Short to Battery Survivability • Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD)
• Low ESD Clamping Voltage (34 V Typical, +8 A TLP, I/O to GND) • SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• USB2.0/3.0 • LVDS • HDMI • High Speed Differential Pairs
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3 12
SC−75 CASE 463
MARKING DIAGRAM
E5 M 1
E5 = Specific Device Code M = Date Code
PIN CONFIGURATION AND SCHEMATIC
Pin 1 Pin 2
Pin 3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +150 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature − Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact
IEC 61000−4−2 Air ISO 10605 Contact (330 pF / 330 W) ISO 10605 Contact (330 pF / 2 kW) ISO 10605 Contact (150 pF / 2 kW)
ESD
±8 kV ±15 ±8 ±20 ±27
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
October, 2017 − Rev. 1
1
Publication Order Number: ESD7102/D
ESD7102, SZESD7102
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max
Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Clamping Voltage (Note 1) Clamping Voltage TLP (Note 2)
VRWM VBR IR VC VC
Dynamic Resistance (Note 2) Junction Capacitance
IR CJ
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
VRWM = 5 V, I/O Pin to GND
IEC61000−4−2, ±8 kV Contact
IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A
TLP Pulse
VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz between I/O Pins and GND
16
16.5
1
See Figures 1 and 2
34 55 −5.3 −10
1.5
0.2 0.4 0.3 0.5
Junction Capacitance Match
DCJ VR = 0 V, f = 1 MHz between I/O1 to GND and I/O 2 to GND
5 10
Insertion Loss
f = 1 GHz f = 3 GHz
0.1 0.2
3dB Bandwidth
fBW
RL = 50 W
5
1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Unit V V mA
V
W pF % dB GHz
120 20
100 0
80 −20
VOLTAGE (V)
60 −40
40 −60
20 −80
0 −100
−20 −25 0 25 50 75 100 125 150 175
TIME (ns) Figure 1. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
−120 −25 0 25 50 75 100 125 150 175
TIME (ns) Figure 2. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
1E−02 1E−03 1E−04 1E−05 1E−06 1E−07 1E−08 1E−09 1E−10
CAPACITANCE (pF)
0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10
1E−11 1E−12
−2 0 2 4 6 8 10 12 14 16 18 20 22 24 VOLTAGE (V)
Figure 3. Typical IV Characteristic Curve
0.05 0 0
2 4 6 8 10 12 14 16 BIAS VOLTAGE (V)
Figure 4. Typical CV Characteristic Curve
VOLTAGE (V)
CURRENT (A)
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ESD7102, SZESD7102
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at 60 ns (A)
2 4 6 8
IEC61000−4−2 Waveform Ipeak 100% 90%
I @ 30 ns
I @ 60 ns
10% Figure 5. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
DUT
Oscilloscope
50 W Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.
ESD Voltage Clamping For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at.