EM48AM3284LBB

Revision History Revision 0.1 (May. 2010) - First release. Revision 0.2 (Sep. 2010) - Delete CL=2 parameters - Input Leakage Current = -2μA ~ +2μA - Change Supply Voltage Rating = -0.5 ~ +2.3 - Delete Deep Power Down Mode - Change AC timing paramters: tRC & tIS Revision 0.3 (Nov. 2010) - Change clock input capacitance value EM48AM3284LBB Nov. 2010 www.eorex.com 1/22 EM48AM3284LBB 512Mb (4M×4Bank×32) Mobile Synchronous DRAM Features Fully Synchronous to Positive Clock Edge VDD= 1.7V~1.95V for 133MHz & 166MHz Power Supply LVCMOS Compatible with Multiplexed Address Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page Programmable CAS Latency (C/L) - 3 Data Mask (DQM) for Read / Write Masking Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) Burst Read with Single-bit Write Operation Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self Refresh) Programmable Driver Strength Control – Full Strength or 1/2, 1/4 of Full Strength Auto Refresh and Self Refresh 8,192 Refresh Cycles / 64ms (7.8us) Description The EM48AM3284LBB is Mobile Synchronous Dynamic Random Access Memory (SDRAM) organized as 4Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 512Mb Mobile SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memo...