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ISLA214P Dataheets PDF



Part Number ISLA214P
Manufacturers Intersil
Logo Intersil
Description ADC
Datasheet ISLA214P DatasheetISLA214P Datasheet (PDF)

14-Bit, 250MSPS/200MSPS/130MSPS ADC ISLA214P The ISLA214P is a series of low power, high performance 14-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA214P is part of a pin-compatible family of 12 to 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as f.

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14-Bit, 250MSPS/200MSPS/130MSPS ADC ISLA214P The ISLA214P is a series of low power, high performance 14-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA214P is part of a pin-compatible family of 12 to 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters, such as gain and offset. Digital output data is presented in selectable LVDS or CMOS formats, and can be configured as full-width, single data rate (SDR) or half-width, double data rate (DDR). The ISLA214P is available in a 72-contact QFN package with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40°C to +85°C). Key Specifications • SNR @ 250/200/130MSPS 73.0/73.8/74.9dBFS fIN = 30MHz 70.6/71.1/70.9dBFS fIN = 363MHz • SFDR @ 250/200/130MSPS 82/88/88dBc fIN = 30MHz 78/82/84dBc fIN = 363MHz • Total Power Consumption = 480mW @ 250MSPS Features • Single supply 1.8V operation • Clock duty cycle stabilizer • 75fs clock jitter • 700MHz bandwidth • Programmable built-in test patterns • Multi-ADC support - SPI programmable fine gain and offset control - Support for multiple ADC synchronization - Optimized output timing • Nap and sleep modes - 200µs sleep wake-up time • Data output clock • SDR/DDR LVDS-compatible or LVCMOS outputs • Selectable clock divider Applications • Radar array processing • Software defined radios • Broadband communications • High-performance data acquisition • Communications test equipment AVDD CLKDIV CLKDIVRSTP CLKDIVRSTN OVDD CLKP CLKN CLOCK MANAGEMENT CLKOUTP CLKOUTN VINP VINN VCM SHA 14-BIT 250 MSPS ADC + – SPI CONTROL DIGITAL ERROR CORRECTION D[13:0]P D[13:0]N Pin-Compatible Family MODEL ISLA216P25 ISLA216P20 ISLA216P13 ISLA214P50 ISLA214P25 ISLA214P20 ISLA214P13 ISLA212P50 ISLA212P25 ISLA212P20 ISLA212P13 RESOLUTION 16 16 16 14 14 14 14 12 12 12 12 SPEED (MSPS) 250 200 130 500 250 200 130 500 250 200 130 AVSS NAPSLP RESETN CSB SCLK SDIO SDO RLVDS OVSS December 5, 2012 FN7572.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISLA214P Pin Configuration - LVDS MODE ISLA214P (72 LD QFN) TOP VIEW AVDD AVDD AVDD SDIO SCLK CSB SDO OVSS ORP ORN OVDD OVSS D0P D0N D1P D1N D2P D2N 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DNC 1 DNC 2 NAPSLP 3 VCM 4 AVSS 5 AVDD 6 AVSS 7 VINN 8 VINN 9 VINP 10 VINP 11 AVSS 12 AVDD 13 AVSS 14 CLKDIV 15 IPTAT 16 DNC 17 RESETN 18 Connect Thermal Pad to AVSS Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing for Physical Dimensions 54 D3P 53 D3N 52 D4P 51 D4N 50 D5P 49 D5N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D6P 43 D6N 42 D7P 41 D7N 40 D8P 39 D8N 38 D9P 37 D9N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AVDD AVDD AVDD CLKP CLKN CLKDIVRSTP CLKDIVRSTN OVSS OVDD D13N D13P D12N D12P OVDD D11N D11P D10N D10P 2 FN7572.2 December 5, 2012 ISLA214P Pin Descriptions - 72 Ld QFN, LVDS Mode PIN NUMBER 1, 2, 17 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 4 8, 9 10, 11 15 16 18 22, 23 24, 25 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 46 47, 48 49 50 51 52 53 54 55 56 57 LVDS PIN NAME DNC AVDD LVDS PIN FUNCTION Do Not Connect 1.8V Analog Supply DDR MODE COMMENTS AVSS OVDD OVSS NAPSLP VCM VINN VINP CLKDIV IPTAT RESETN CLKP, CLKN CLKDIVRSTP, CLKDIVRSTN D13N D13P D12N D12P D11N D11P D10N D10P D9N D9P D8N D8P D7N D7P D6N D6P RLVDS CLKOUTN, CLKOUTP D5N D5P D4N D4P D3N D3P D2N D2P D1N Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement LVDS Bit 13(MSB) Output Complement LVDS Bit 13 (MSB) Output True LVDS Bit 12 Output Complement LVDS Bit 12 Output True LVDS Bit 11 Output Complement LVDS Bit 11 Output True LVDS Bit 10 Output Complement LVDS Bit 10 Output True LVDS Bit 9 Output Complement LVDS Bit 9 Output True LVDS Bit 8 Output Complement LVDS Bit 8 Output True LVDS Bit 7 Output Complement LVDS Bit 7 Output True LVDS Bit 6 Output Complement LVDS Bit 6 Output True LVDS Bias Resistor (Connect to OVSS with 1% 10kΩ) LVDS Clock Output Complement, True LVDS Bit 5 Output Complement LVDS Bit 5 Output True LVDS Bit 4 Output Complement LVDS Bit 4 Output True LVD.


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