5P49V5933 Clock Generator Datasheet

5P49V5933 Datasheet, PDF, Equivalent


Part Number

5P49V5933

Description

Programmable Clock Generator

Manufacture

Integrated Device Technology

Total Page 30 Pages
Datasheet
Download 5P49V5933 Datasheet


5P49V5933
Programmable Clock Generator
5P49V5933
DATASHEET
Description
The 5P49V5933 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock® 5).
5P49V5933 by default uses an integrated 25MHz crystal as
input reference. It also has a redundant external clock input.
A glitchless manual switchover functions allows selection of
either one as mentioned above as input reference during
normal operation
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
NC
NC
VDDA
CLKSEL
1 24 23 22 21 20 1918
2 17
3 16
EPAD
4 15
5 14
6 13
7 8 9 10 11 12
VDDA
NC
NC
VDDA
NC
NC
4 × 4 mm 24-LGA
Features
Generates up to two independent output frequencies
High-performance, low-phase noise PLL, < 0.7ps RMS
typical phase jitter on outputs:
– PCIe Gen1–3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
Two fractional output dividers (FODs)
Independent spread spectrum capability on each output
pair
Two banks of internal non-volatile in-system programmable
or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
Input frequency ranges:
– LVDS, LVPECL, HCSL differential clock input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
4 x 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
5P49V5933 NOVEMBER 1, 2017
1 ©2017 Integrated Device Technology, Inc.

5P49V5933
5P49V5933 DATASHEET
Functional Block Diagram
OSC
25MHz
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control Logic
Typical Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1GbE and 10GbE
PLL
FOD1
FOD2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
PROGRAMMABLE CLOCK GENERATOR
2
NOVEMBER 1, 2017


Features Programmable Clock Generator 5P49V5933 DATASHEET Description The 5P49V5933 i s a programmable clock generator intend ed for high performance consumer, netwo rking, industrial, computing, and data- communications applications. Configurat ions may be stored in on-chip One-Time Programmable (OTP) memory or changed us ing I2C interface. This is IDTs fifth g eneration of programmable clock technol ogy (VersaClock® 5). 5P49V5933 by defa ult uses an integrated 25MHz crystal as input reference. It also has a redunda nt external clock input. A glitchless m anual switchover functions allows selec tion of either one as mentioned above a s input reference during normal operati on Two select pins allow up to 4 differ ent configurations to be programmed and accessible using processor GPIOs or bo otstrapping. The different selections m ay be used for different operating mode s (full function, partial function, par tial power-down), regional standards (U S, Japan, Europe) or system production margin testing. The devi.
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