DatasheetsPDF.com

ICS8714008I Dataheets PDF



Part Number ICS8714008I
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description Zero Delay Buffer/ Clock Generator
Datasheet ICS8714008I DatasheetICS8714008I Datasheet (PDF)

FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet ICS8714008I DATASHEET General Description The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for “zero delay” clock regeneration. In PCI Express and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the eight output pairs can be independen.

  ICS8714008I   ICS8714008I


Document
FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet ICS8714008I DATASHEET General Description The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for “zero delay” clock regeneration. In PCI Express and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the eight output pairs can be independently set for either 100MHz or 125MHz. With an output frequency range of 98MHz to 165MHz, the device is also suitable for use in a variety of other applications such as Fibre Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the same board as the ICS8714008I) or remote via a backplane connector. In output mode, an input from a local reference clock applied to the CLK, nCLK input pins is translated to M-LVDS and driven out to the MLVDS, nMLVDS pins. In input mode, the internal M-LVDS driver is placed in High-impedance state using the OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input (e.g. from a backplane). The ICS8714008I uses very low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package (8mm x 8mm). Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (MLVDS, nMLVDS) • Output frequency range: 98MHz - 165MHz • Input frequency range: 19.6MHz - 165MHz • VCO range: 490MHz - 660MHz • PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant • External feedback for “zero delay” clock regeneration • RMS phase jitter @ 125MHz (1.875MHz – 20MHz): 0.59ps (typical) • Full 3.3V supply mode • -40°C to 85°C ambient operating temperature • Lead-free (RoHs 6) packaging Pin Assignment PDIV1 PDIV0 nCLK CLK VDDA QDIV4 QDIV5 QDIV6 QDIV7 Q0 nQ0 VDD Q1 nQ1 VDD OE_MLVDS MLVDS nMLVDS GND PLL_SEL VDD nc FBO_DIV MR OE0 OE1 OE2 GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 11 32 12 31 13 30 14 29 15 17 18 21 24 25 27 28 VDD Q2 nQ2 Q3 nQ3 VDD Q4 nQ4 Q5 nQ5 FBOUT nFBOUT VDD IREF FBI_DIV0 nFBIN FBIN QDIV0 QDIV1 Q7 nQ7 Q6 nQ6 ICS8714008DKI REVISION A NOVEMBER 25, 2013 ICS8714008I 56-Lead VFQFN 8mm x 8mm x 0.925mm package body 4.5mm x 5.2mm ePad size K Package Top View 1 ©2013 Integrated Device Technology, Inc. ICS8714008I DATA SHEET FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET Block Diagram MR1 PDIV1 PDIV0 CLK nCLK MR1 OE_MLVDS MLVDS nMLVDS Pulldown Pulldown Pulldown Pulldown PU/PD Pulldown Pullup PDIV1:0 00 ÷4 (default) 01 ÷5 10 ÷8 11 ÷1 FBI_DIV1 FBI_DIV0 FBIN nFBIN Pullup Pullup Pulldown PU/PD MR1 Pulldown PLL_SEL MR1 Pullup Pulldown FBI_DIV1:0 00 ÷1 01 ÷2 10 ÷4 11 ÷5 (default) QDIV0 0 ÷4 (default) 1 ÷5 3 OE2:0 (PU:PU) QDIV0 (PD) Q0 nQ0 0 PD VCO 490-660MHz 1 QDIV7 0 ÷4 (default) 1 ÷5 FBO_DIV 0 ÷4 (default) 1 ÷5 8 total HCSL Output pairs QDIV7 (PD) Q7 nQ7 FBO_DIV (PD) FBOUT nFBOUT IREF 1One Master Reset pin (MR) is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram easier to read. PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven) PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven) ICS8714008DKI REVISION A NOVEMBER 25, 2013 2 ©2013 Integrated Device Technology, Inc. ICS8714008I DATA SHEET FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 7, 30, 37, 42, 45 VDD Power Core supply pins. 2 OE_MLVDS Input Pullup Active High Output Enable. When HIGH, the M-LVDS output driver is active and provides a buffered copy of reference clock applied the CLK, nCLK input to the MLVDS, nMLVDS output pins. The MLVDS, nMLVDS frequency equals the CLK, nCLK frequency divided by the PDIV Divider value (selectable ÷1, ÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is placed into a High-impedance state and the MLVDS, nMLVDS pins can accept a differential input. LVCMOS/LVTTL interface levels. 3 MLVDS I/O Non-Inverting M-LVDS input/output. The input/output state is determined by the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input and can accept the following differential input levels: M-LVDS, LVDS, LVPECL, .


ICS87001I-01 ICS8714008I ICS8745BI-21


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)