ICS87974I

ICS87974I LOW SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources. Guaranteed low jitter and output skew characteristics make the ICS87974I ideal for those applications demanding well defined performance and repeatability. FEATURES Fully integrated PLL Fifteen single ended 3.3V LVCMOS/LVTTL outputs Two LVCMOS/LVTTL clock inputs for redundant clock applications CLK0 and CLK1 accepts the following input levels: LVCMOS/LVTTL Output frequency range: 8.33MHz to 125MHz VCO range: 200MHz to 500MHz External feedback for ”zero delay” clock regeneration Cycle-to-cycle jitter: ±100ps (typical) Output skew: 350ps (maximum) 3.3V operating supply -40°C to 85°C ambient operating temperature Available in both standard and lead-free RoHS-compliant packages PIN ASSIGNMENT QB0 VDDOB nc GND QC3 VDDOC QC2 GND QC1 VDDOC QC0 GND VCO_SEL GND nMR/OE CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK0 CLK1 nc VDD VDDA 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 ...