Document
SOT457
PUSB2X4D
ESD protection for high-speed interfaces
Rev. 1 — 5 November 2013
Product data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as USB 2.0 ports against ElectroStatic Discharge (ESD).
The device includes four high-level ESD protection diode structures for high-speed signal lines. It is encapsulated in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package.
All signal lines are protected by a special diode configuration offering ultra low line capacitance of 0.85 pF maximum. This configuration provides protection to downstream components from ESD voltages up to 12 kV contact according to IEC 61000-4-2, level 4.
1.2 Features and benefits
System ESD protection for USB 2.0 All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of 12 kV according to IEC 61000-4-2, level 4 Line capacitance of 0.85 pF maximum for each channel
1.3 Applications
The device is designed for receiver and transmitter port protection in: Portable devices TVs, monitors DVD recorders and players Notebooks, mother boards, graphic cards and ports Set-top boxes and game consoles
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
2. Pinning information
Table 1. Pin 1 2 3 4 5 6
Pinning Description ESD protection for I/O signals ground ESD protection for I/O signals ESD protection for I/O signals n.c. ESD protection for I/O signals
Simplified outline
654
Graphic symbol
13
46
123
2
018aaa176
3. Ordering information
Table 2. Ordering information
Type number Package
Name
Description
PUSB2X4D
SC-74
plastic surface-mounted package; 6 leads
Version SOT457
4. Marking
Table 3. Marking codes Type number PUSB2X4D
Marking code DE
5. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VI VESD
input voltage
electrostatic discharge voltage
pins 1, 3, 4 and 6 to ground; IEC 61000-4-2, level 4
0.5
contact discharge
12
air discharge
15
Tamb Tstg
ambient temperature storage temperature
40 55
Max Unit +5.5 V
+12 +15 +85 +125
kV kV C C
PUSB2X4D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
6. Characteristics
Table 5. Characteristics Tamb = 25 C unless otherwise specified.
Symbol Parameter
Conditions
VBR IRM VF Cline
Cline
breakdown voltage reverse leakage current forward voltage line capacitance
line capacitance difference
II = 1 mA per channel; VI = 5 V II = 1 mA f = 1 MHz
VI = 0 V VI = 2.5 V f = 1 MHz; VI = 2.5 V
rdyn
dynamic resistance
surge
positive transient
negative transient
TLP
positive transient
negative transient
VCL clamping voltage
positive transient IPP = 4.8 A
negative transient
IPP = 5.2 A
[1] This parameter is guaranteed by design. [2] According to IEC 61000-4-5 (8/20 s current waveform). [3] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns.
Min 6 -
[1]
[1] -
[2]
-
[3]
-
[2]
-
-
Typ Max Unit
- 9V
- 1 A
0.7 -
V
0.7 0.85 pF 0.6 0.75 pF - 0.1 pF
0.41 0.34 -
0.48 0.34 -
4.3 -
2.7 -
V
V
PUSB2X4D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 November 2013
© NXP B.V. 2013. All rights reserved.
3 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
0
S21 (dB)
-2
aaa-009805
-4
-6
-8
-10 1
10 102 103 104 f (MHz)
Fig 1. Insertion loss; typical values
1.2 a
0.8
0
S21 (dB)
-30
aaa-009806
-60
-90 10
102 103 104 f (MHz)
Fig 2. Crosstalk; typical values
aaa-009807
0.4
0 012345 VI (A)
Fig 3.
a = -----------C----l--i--n--e-----------ClineVI = 0 V
Relative capacitance as a function of input voltage; typical values
PUSB2X4D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 November 2013
© NXP B.V. 2013. All rights reserved.
4 of 11
NXP Semiconductors
PUSB2X4D
ESD protection for high-speed interfaces
6
IPP (A)
4
aaa-009808
0
IPP (A)
-2
aaa-009809
2 -4
0 012345 VCL (V)
Fig 4.
IEC 61000-4-5; tp = 8/20 s; positive pulse
Dynamic resistance with positive clamping; typical values
15
I (A)
12
aaa-009810
-6 -3 -2 -1 0 VCL (V)
Fig 5.
IEC 61000-4-5; tp = 8/20 s; negative pulse
Dynamic resistance with negative clamping, typical values
0
I (A)
-3
aaa-009811
9 -6
6 -9
3 -12
0 0 4 8 12 VCL (V)
Fig 6.
tp = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with positive clamping, typical values
-15 -8 -6 -4 -2 0 VCL (V)
Fig 7.
tp = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with negative clamping; typical values
The device uses an advanced clamping structure, which shows a negative dynamic resistance. This snap-back behavior strongly r.