Document
ESD9D5.0S
Transient Voltage Suppressors
ESD Protection Diodes with Ultra−Low Capacitance
The ESD9D5.0 is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications.
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PIN 1. CATHODE 2. ANODE
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Specification Features:
• Ultra Low Capacitance 0.6 pF • Low Clamping Voltage • Small Body Outline Dimensions:
0.039″ x 0.024″ (1.00 mm x 0.60 mm)
• Low Body Height: 0.016″ (0.4 mm) • Stand−off Voltage: 5 V • Low Leakage • Response Time is Typically < 1.0 ns • IEC61000−4−2 Level 4 ESD Protection • This is a Pb−Free Device
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1 SOD−923 CASE 514AB
MARKING DIAGRAM
1
BB M
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Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V−0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any QUALIFIED MAX REFLOW TEMPERATURE: 260°C Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating
Symbol
IEC 61000−4−2 (ESD)
Contact Air
Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C
Storage Temperature Range
Junction Temperature Range
Lead Solder Temperature − Maximum (10 Second Duration)
°PD°
Tstg TJ TL
Value
±8 ±8
150
Unit kV
mW
−55 to +150 −55 to +125
260
°C °C °C
BB = Specific Device Code M = Date Code
ORDERING INFORMATION
Device
Package
Shipping†
ESD9D5.0ST5G SOD−923 8000/Tape & Reel (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking column of the Electrical Characteristics tables starting on page 2 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 1
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Publication Order Number: ESD9D5.0S/D
ESD9D5.0S
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
IPP Maximum Reverse Peak Pulse Current
VC Clamping Voltage @ IPP VRWM Working Peak Reverse Voltage
IR Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT
IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters.
I IPP
VC VBR VRWM IIRT IIRT VRWM VBR VC V
IPP Bi−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Device ESD9D5.0ST5G
Device Marking
BB
VRWM (V)
Max 5.0
IR (mA) @ VRWM
Max 1.0
VBR (V) @ IT (Note 2)
Min 5.4
IT C (pF)
mA Typ Max 1.0 0.6 0.9
VC (V) @ IPP = 1 A
(Note 3)
Max 13.5
VC
Per IEC61000−4−2 (Note 4)
Figures 1 and 2 See Below
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C. 3. Surge current waveform per Figure 5.
4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2
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ESD9D5.0S
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at 60 ns (A)
2
4 6 8
IEC61000−4−2 Waveform Ipeak 100% 90%
I @ 30 ns
I @ 60 ns
10% Figure 3. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.
ESD Voltage Clamping For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across .