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RTM560-266R Dataheets PDF



Part Number RTM560-266R
Manufacturers RealTek
Logo RealTek
Description Clock Generator
Datasheet RTM560-266R DatasheetRTM560-266R Datasheet (PDF)

Clock Generator General Description The RTM 560-266R is a single chip frequency generator for VIA KT266 system. The clock chip provides standard serial bus for programming device function. Based on the function above, the spread spectrum can be enable for reducing EMI. And RTM 560-266R also builds in the testability function. Features ! Support Up to 200 MHz frequency. ! Power Down feature. ! Spread Spectrum for EMI control. ! Output features: " 1 pairs – CPU differential open drain. " 1 pair.

  RTM560-266R   RTM560-266R


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Clock Generator General Description The RTM 560-266R is a single chip frequency generator for VIA KT266 system. The clock chip provides standard serial bus for programming device function. Based on the function above, the spread spectrum can be enable for reducing EMI. And RTM 560-266R also builds in the testability function. Features ! Support Up to 200 MHz frequency. ! Power Down feature. ! Spread Spectrum for EMI control. ! Output features: " 1 pairs – CPU differential open drain. " 1 pairs - CPU [email protected]. " 11- PCI @3.3V. " 1- 48MHz, @3.3V fixed. " 1- 24_48# MHz, @3.3V fixed. " 3- REF @3.3V, 14.318MHz. " 3- AGP @3.3V VDD_3.3 GND X1 X2 VDD_3.3 FS2*/48MHz FS3*/24_48MHz GND FS4*/PCIF PCI0/*SEL24/48# PCI1 GND PCI2 PCI3 VDD_3.3 PCI4 PCI5 PCI6 GND PCI7 PCI8 PCI9_E VDD_3.3 SRESET# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RTM560-266 R 48 FS0*/REF0 47 FS1*/REF1 46 REF2 45 REF_STOP# 44 AGP_STOP# 43 GND 42 CPUCLKT0 41 CPUCLKC0 40 VDD_2.5 39 CPUCLKT_CS 38 CPUCLKC_CS 37 GND 36 CPU_STOP# 35 PCI_STOP# 34 PD# 33 VDD_3.3 32 GND 31 SDATA 30 SCLK 29 GND 28 AGP2 27 AGP1 26 AGP0 25 VDD_3.3 X1 X2 sclk sdata CONTROL PIN XTAL OSC Serial bus interface PLL1 PLL2 DIVIDER MULTIPLEX REF OUTPUT DELAY STOP TRISTATE CLOCK OUTPUT CONTROL LOGIC 01/04/13 -1- Clock Generator RTM DDR solution : RTM560-250R+RTM580-251R(4DDR/2SDR) (2DDR+2SDR) SSOP-48 RTM560-250R+RTM580-256R(4DDR/2SDR) (3DDR+2SDR) SSOP-56 RTM560-250R+RTM580-255R(4DDR/3SDR) (2DDR+3SDR) SSOP-48 RTM560-250R+RTM580-228R(2DDR/3SDR) SSOP-28 01/04/13 -2- Clock Generator Pin Description Pin Name PIN Type REF_0/FS0* 48 I/O REF_1/FS1* 47 I/O REF_2 X1 X2 PCIF/FS4* 46 3 4 9 O I O O PCI-E 22 PCI0/SEL24_48# 10 O I/O PCI 1:8 SRESET# 48MHz/FS2* 11, 13, 14, 16, 17, 18, 20, 21 24 6 O OD I/O 24_48MHz/FS3* 7 I/O PD# * PCI_STOP# * 34 35 I I Description Reference Clock0 /Frequency Selection 0: 3.3V 14.318 MHz clock output. This pin also serves as the select strap to determine device’s operating frequency as described in frequency Table. Pull high 120k. Reference Clock1 /Frequency Selection 1: 3.3V 14.318 MHz clock output. This pin also serves as the select strap to determine device’s operating frequency as described in frequency Table. Pull high 120k. Reference Clock2: 3.3V 14.318 MHz clock output. Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock Free running /Frequency Selection 4 : 3.3V 33 MHz PCI clock outputs. Not affected by PCI_STOP#. This pin also serves as the select strap to determine device’s operating frequency as described in frequency Table. Pull high 120k. Early PCI Clock: Lead 2 ns than general PCI bus clock PCI Clock 0/SEL24_48#: 3.3V 33 MHz PCI clock output. This pin also serves as power-on latch for 24_48MHz frequency selection, “0” for 48MHz and “1” for 24MHz. PCI Clock 1 through 8: 3.3V 33 MHz PCI clock outputs. PCI0:7. SRESET#: Reset output for watch dog & bounding option( open drain pad). 48 MHz Clock Output/Frequency Selection 2: 3.3V fixed 48 MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device’s operating frequency as described in frequency Table. Pull high 120k. 24 MHz Clock Output/Frequency Selection 3: 3.3V fixed 24 MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device’s operating frequency as described in frequency Table. Pull high 120k. Power Down Control: LVTTL compatible input that places the device in power down mode when held low. Pull high 120k. PCI stop Control: Stop all PCI clock except PCI-F when held low. Pull high 120k. CPU_STOP# * 36 I CPU stop Control: Stop all CPU clock when held low. Pull high 120k. AGP_STOP# * 44 I AGP stop Control: Stop all AGP clock when held low. Pull high 120k. REF_STOP# * 45 I REF stop Control: Stop all REF clock when held low. Pull high 120k. AGP0:2 CPUCLKC_CS CPUCLKT_CS CPUCLKC0 CPUCLKT0 SDATA SCLK VDD3.3 VDD2.5 GND 26, 27, 28 38, 39 O O 41, 42 OD 31 30 1, 5, 15, 23, 25, 33 40 I/O I P P 2, 8, 12, 19, G 29, 32, 37, 43 AGP Clock Outputs: 3.3V output clocks. The operating frequency is controlled by FS0:3. CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:3. Voltage swing is set by VDD2.5.(PUSH/PULL) CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS 0:4. Voltage swing is set by VDD2.5.(OPEN_DRAIN) Data pin for serial interface. Clock pin for serial interface. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output buffers. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU outp.


C2695 RTM560-266R CY28323


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