P3P622S01J

P3P622S01J Timing-Safet Peak EMI Reduction IC Functional Description P3P622S01J is a versatile, 3.3 V Zero−delay buffer designed to distribute low frequency Timing−Safe Clocks with Peak EMI Reduction. P3P622S01J accepts an input clock either from a fundamental Crystal or from an external reference clock. P3P622S01J accepts one reference input and drives out two low−skew clocks. P3P622S01J has an on−chip PLL that locks to an input reference clock. The PLL feedback is on−chip and is obtained from the CLKOUT pad, internal to the device. Multiple P3P622S01J devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 700 pS. The output has less than 200 pS of cycle−to−cycle jitter. The input and output propagation delay is guaranteed to be less than 250 pS, and the output−to−output skew is guaranteed to be less than 250 pS. Refer “Spread Spectrum Control and Input−Output Skew Table” for deviations and Input−Output Skew. General Features Low Frequency Clock Distribution with Timing−Safe Peak EMI Reduction Input Frequency Range: 4 MHz − 20 MHz Zero Input − Output Propagation Delay Low−skew Outputs: ♦ Output−output Skew Less than 250 pS ♦ Device−device Skew Less than 700 pS Less than 200 pS Cycle−to−cycle Jitter Available in 8 Pin, 4.4 mm TSSOP Package Supply Voltage: 3.3 V ± 0.3 V These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com TSSOP8 ...