Document
P3PSL450A
Low Voltage, Timing-Safe] Peak EMI Reduction IC
Functional Description P3PSL450A/AH is a versatile low voltage peak EMI reduction IC
based on Timing−Safe technology. P3PSL450A/AH accepts one input from an external reference, and locks on to it delivering a 1x Timing−Safe output clock. P3PSL450A/AH has a Frequency Selection (FS) control that facilitates selecting one of the two frequency ranges within the operating frequency range. Refer frequency Selection table. The device has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected at this pin to GND. P3PSL450A/AH has an MR pin for selecting one of the two Modulation Rates. PD# provides the Power Down option.
P3PSL450A is a Low drive part and P3PSL450AH is a High drive part. Refer to DC/AC Electrical characteristic table.
P3PSL450A/AH operates over a supply voltage range of 1.8 V $ 0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
General Features
• 1x, LVCMOS Timing−Safe Peak EMI Reduction • Input Clock Frequency: 15 MHz − 60 MHz • Output Clock Frequency (Timing−Safe): 15 MHz − 60 MHz • Analog Frequency Deviation Selection • Two different Modulation Rate Selection Option • Power Down option for Power Save • Low and High Drive Parts • Supply Voltage: 1.8 V $ 0.2 V • 8 Pin WDFN (2 mm X 2 mm) Package • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Application
• P3PSL450A/AH is targeted for use in consumer electronic
applications like mobile phones, Camera modules, MFP and DPF
MR VDD SSEXTR
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1
WDFN8 CASE 511AQ
MARKING DIAGRAM
1 XX MG G
XX = Specific Device Code M = Date Code G = Pb−Free Device
PIN CONFIGURATION
CLKIN 1 FS 2
PD# 3 GND 4
8 VDD 7 SSEXTR 6 MR 5 ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
CLKIN
PLL
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 1
PD# GND
FS
Figure 1. Block Diagram
1
ModOUT (Timing−Safe)
Publication Order Number: P3PSL450A/D
P3PSL450A
Table 1. PIN DESCRIPTION
Pin # Pin Name
Type
1 CLKIN
I
2 FS
I
3 PD#
I
4 GND
P
5 ModOUT O
6 MR
I
7 SSEXTR 8 VDD
I P
Description External reference Clock input. Frequency Select. Has an internal pull−down resistor. see Frequency Selection table Power Down. Pull LOW to enable Power Down. Pull HIGH to disable power down. Output Clock will be LOW when power down is enabled. Has an internal pull−up resistor Ground Buffered modulated Timing−Safe clock output Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pull−up resistor. Analog Frequency Deviation Selection through external resistor to GND. 1.8 V Supply Voltage
Table 2. FREQUENCY SELECTION TABLE FS 0 1
Frequency (MHz) 15−30 30−60
Table 3. ABSOLUTE MAXIMUM RATING
Parameter
Min Max Unit
Supply Voltage to Ground Potential
−0.3 +2.7 V
DC Input Voltage(CLKIN)
−0.3 +2.7 V
DC Input Voltage (Except CLKIN) Storage Temperature
−0.3 −65
VDD + 0.3 +150
V °C
Max. Soldering Temperature (10 sec)
260 °C
Junction Temperature
150 °C
Static Discharge Voltage (As per JEDEC STD22−A114−B)
2000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. OPERATING CONDITIONS Symbol VDD Supply Voltage TA Operating Temperature CL Load Capacitance CIN Input Capacitance
Parameter
Min Max Unit 1.6 2 V −20 +85 °C
15 pF 7 pF
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P3PSL450A
Table 5. DC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Symbol
Parameter
Test Conditions
Min Typ Max Unit
VDD
Supply Voltage
1.6 1.8
2
V
VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current VOH Output HIGH Voltage
VOL Output LOW Voltage
ICC Static Supply Current IDD Dynamic Supply Current
0.65 * VDD
V
0.35 * VDD
V
VIN = VDD
5 mA
VIN = 0 V
5 mA
IOH = −8 mA (P3PSL450A)
0.75 * VDD
V
IOH = −16 mA (P3PSL450AH)
IOL = 8 mA (P3PSL450A)
0.25 * VDD
V
IOL = 16 mA (P3PSL450AH)
CLKIN & PD# pins pulled to GND
10 mA
Unloaded Output
FS = 0, @ 15 MHz FS = 0, @ 30 MHz
1.7 2.2 mA 3.0 3.7
FS = 1, @ 30 MHz
2.6 3.7
FS = 1, @ 60 MHz
4.3 6.4
Zo Output Impedance
P3PSL450A P3PSL450AH
23 W 17
Table 6. AC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Parameter
Test Conditions
Min
Input Frequency
FS = 0
15
FS = 1
30
ModOUT
FS = 0
15
FS = 1
30
Duty Cycle (Notes 1 and 2)
Measured at VDD / 2
45
Rise Time (Notes 1 and 2)
Measured between 20% to 80%
P3PSL450A P3PSL450AH
Fall Time (Notes 1 and 2)
Measured between 80% to 20%
P3PSL450A P3PSL450AH
Cycle−to−Cycle Jitter (Note 2)
Unloaded output with SSEXTR pin OPEN
FS = 0
15 MHz 24 MHz
30 MHz
FS = 1
30 MHz
60 MHz
PLL.