74ALVC16240

74ALVC16240 Low−Voltage 1.8/2.5/3.3 V 16−Bit Buffer With 3.6 V−Tolerant Inputs and Outputs (3−State, Inverting) The 74ALVC16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The 74ALVC16240 is nibble controlled with each nibble functioning identically, but independently. The control pins may be tied together to obtain full 16−bit operation. The 3−state outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are in the high impedance state. Designed for Low Voltage Operation: VCC = 1.65−3.6 V 3.6V Tolerant Inputs and Outputs High Speed Operation: 3.0 ns max for 3.0 to 3.6 V 3.7 ns max for 2.3 to 2.7 V 6.0 ns max for 1.65 to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±12 mA Drive at 2.3 V ±4 mA Drive at 1.65 V Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V† Near Zero Static Supply Current in All Three Logic States (40 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V; Machine Model >200 V Second Source to Industry Standard 74ALVC16240 †To ensure the outputs activate in the 3−state condition, the output enable pins should be connected to VCC through a pull−up resistor. The value of the resistor is determined by the current sinking capabili...