NE522

NE522 High−Speed Dual−Differential Comparator/Sense Amp Features 15 ns Maximum Guaranteed Propagation Delay 20 mA Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input Voltage Range Operates from Standard Supply Voltages Applications MOS Memory Sense Amp A-to-D Conversion High-Speed Line Receiver INPUT 1A INPUT 1B (1) (2) (4) OUTPUT 1Y STROBE 1G STROBE S (5) (6) (12) INPUT 2A (11) INPUT 2B (9) OUTPUT 2Y (8) STROBE 2G Figure 1. Block Diagram LOGIC FUNCTION TABLE VID (A+, B−) < −VOS −VOS < VID < VOS > VOS X X STRS H H H L X STRG H H H X L Output Transistor ON Undefined OFF OFF OFF http://onsemi.com SOIC−14 D SUFFIX CASE 751A 14 1 MARKING DIAGRAMS 14 NE522 AWLYWW 1 PDIP−14 N SUFFIX CASE 646 NE522N AWLYYWW 14 1 A WL YY, Y WW = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS D, N Packages INPUT 1A 1 INPUT 1B 2 NC 3 OUTPUT 1Y 4 STROBE 1G 5 STROBE S 6 GROUND 7 14 V+ 13 V− 12 INPUT 2A 11 INPUT 2B 10 NC 9 OUTPUT 2Y 8 STROBE 2G (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 0 1 Publication Order Number: NE522/D NE522 V+ 14 − 2 1+ 13 V 12 + 11 − 13 V− R2 R1 Q2 Q2 Q4 Q3 D7 D6 R17 R16 Q6 Q5 5 Q9 R4 R8 Q16 Q10 Q8 Q13 Q11 R5 R3 R15 R6 R10 Q18 R7 Q17 R9 Q19 R14 D2 D3 Q15 Q14 R12 R11 D4 D5 Q20 Q21 Q22 Q23 R18 R19 8 Q24 Fig...