Document
LC05112CMT
CMOS LSI
1-Cell Lithium-Ion Battery Protection IC with integrated Power MOS FET
http://onsemi.com
Overview
The LC05112CMT is a protection IC for 1-cell lithium-ion secondary batteries with integrated power MOS FET. Also it integrates highly accurate detection circuits and detection delay circuits to prevent batteries from over-charging, over-discharging, over-current discharging and over-current charging. A battery protection system can be made by only LC05112CMT and few external parts..
WDFN6 2.6x4.0, 0.65P, Dual Flag
Feature
Charge-and-discharge power MOSFET are integrated at Ta = 25C, VCC = 4.5V
ON resistance (total of charge and discharge) 11.2m (typ)
Highly accurate detection voltage/current at Ta = 25C, VCC = 3.7V
Over-charge detection
±25mV
Over-discharge detection
±50mV
Charge over-current detection
±0.7A
Discharge over-current detection ±0.7A
Delay time for detection and release (fixed internally)
Discharge/Charge over-current detection is compensated for temperature dependency of power FET.
0V battery charging
: “Unavailable”
Over charge detection voltage
: 4.0V to 4.5V (5mV steps)
Over charge release hysteresis
: 0V to 0.3V (100mV steps)
Over discharge detection voltage
: 2.2V to 2.8V (50mV steps)
Over discharge release hysteresis
: 0V to 0.075V (25mV steps)
Discharge over current detection
: 2.0A to 8.0A (0.5A steps)
Charge over current detection
: 8.0A to -2.0A (0.5A steps)
Over-discharge detection delay time
: 20ms or 128ms
Typical Applications
Smart phone Tablet Wearable device
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2014 September 2014 - Rev. 1
1
Publication Order Number : LC05112CMT/D
LC05112CMT
Specifications Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
S1 - S2 voltage
CS terminal Input voltage
Charge or discharge current
TST Input voltage
Storage temperature Current between S1 and S2(DC) Current between S1 and S2 (continuous pulse) Operating ambient temperature
Symbol VCC
VS1-S2 CS
BAT-, PACTST Tstg ID
IDP Topr
Ratings -0.3-12.0
24.0 VCC24.0
10.0 -0.3-7 55 to +125 10.0
35 40 to +85
Allowable power dissipation
Pd
350
Junction temperature
Tj 125
Unit V V V A V C A
A C mW C
Conditions Between PAC+ and VCC : R1=680
VCC = 3.7V Pulse Width<10s, duty cycle<1%
Glass epoxy four-layer board. Board size 27.4mm x 3.1mm x 0.8mm
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded even for a moment. Caution 2) If you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature
change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
Example of Application Circuit
Components R1
Recommended value
680
MAX 1k
unit
Description
R2 1k 2k
C1
2.2
4.7u F
* We don’t guarantee the characteristics of the circuit shown above.
* TST pin would be better to be connected to VSS pin, though it is connected to VSS with internal resistor (100k typ).
http://www.onsemi.com
2
LC05112CMT
Electrical Characteristics at Ta = 25C, unless otherwise specified.
Parameter
Detection voltage
Over-charge detection voltage Over-charge release voltage Over-discharge detection voltage
Over-discharge release voltage
Discharge over-current detection current Discharge over-current release current Discharge over-current detection current (Short circuit) Charge over-current detection current Charge over-current release current
Input voltage 0 V battery charge inhibition battery voltage Current consumption
Operating current
Shutt down current
Resistance
ON resistance 1 of integrated power MOS FET ON resistance 2 of integrated power MOS FET ON resistance 3 of integrated power MOS FET ON resistance 4 of integrated power MOS FET Internal resistance (VCC-CS)
Internal resistance (VSS-CS)
Detection and Release delay time
Over-charge detection delay time Over-charge release delay time Over-discharge detection delay time Over-discharge release delay time Discharge over-current detection delay time 1 Discharge over-current release delay time 1 Discharge over-current detection delay time 2 (Short circuit) Charge Over-current detection delay time Charge Over-current release delay time
Symbol
Vov Vovr Vuv Vuvr Ioc Iocr Ioc2 Ioch Iochr
Vinh
Icc Ishutt
Ron1 Ron2 Ron3 Ron4 Rcsu Rcsd
Tov Tovr Tuv Tuvr Toc1 Tocr1
Toc2
Toch Tochr
MIN. Vov_set -25 Vovr_set -40 Vuv_set -50 Vuvr_set -100 Ioc_set -0.7 Ioc_set-0.7
14.7 Ioch_set -0.7 Ioch_set-0.7
0.4
10.4 9.6 9.2 8.8
0.8 12.8 102 16 0.9 9.6 3.2
80
12.8 3.2
.