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AN921 Dataheets PDF



Part Number AN921
Manufacturers Silicon Laboratories
Logo Silicon Laboratories
Description Configurable Logic Unit
Datasheet AN921 DatasheetAN921 Datasheet (PDF)

AN921: Configurable Logic Unit The EFM8LB1 and EFM8BB3 family of MCUs contain Configurable Logic Units (CLUs) that can be applied to applications that require some form of programmable logic. This document demonstrates how to use CLUs to implement the following functions: • SR latch • D latch • Button debounce • Manchester encoder/decoder • Biphase Mark encoder/decoder KEY POINTS • Configurable Logic operates without CPU intervention. • Each unit supports 256 different combinatorial logic func.

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AN921: Configurable Logic Unit The EFM8LB1 and EFM8BB3 family of MCUs contain Configurable Logic Units (CLUs) that can be applied to applications that require some form of programmable logic. This document demonstrates how to use CLUs to implement the following functions: • SR latch • D latch • Button debounce • Manchester encoder/decoder • Biphase Mark encoder/decoder KEY POINTS • Configurable Logic operates without CPU intervention. • Each unit supports 256 different combinatorial logic functions, such as AND, OR, XOR, and multiplexing. • Multiple units combined can implement latches, encoders, and decoders. External Pins Timer Overflow Pulses PCA Channels CLU Asynch Outputs External Pins ADC0 ADBUSY Flag PCA Channels CLU Asynch Outputs Carry from CLU[n-1] (CLU3 carries to CLU0) SYSCLK Timer Overflow (ALTCLK) Input Mux A Input Mux B CnEN CnEN CnEN FNSEL CLUn Carry to CLU[n+1] Look Up Table (LUT) OEN CnEN CnEN DQ CE CLR Q RST Output Selection SYSCLK CLUnOUT Asynchronous Output (to other CLUs) CnOUTa Synchronizer Synchronous Output (to peripherals) CnOUT Clock Polarity Clock Selection silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 AN921: Configurable Logic Unit Configurable Logic Overview 1. Configurable Logic Overview The configurable logic module provides multiple blocks of user-programmed digital logic that operate without CPU intervention. In the EFM8LB1 and EFM8BB3 families, the configurable logic (CL) module contains of four independent configurable logic units (CLUs) that support user-programmable asynchronous and synchronous Boolean logic operations. A number of internal and external signals may be used as inputs to each CLU, and the outputs may be routed out to port I/O pins or directly to select peripheral inputs. Each CLU has a look up table (LUT) logic function that can be used to provide up to 256 different functions for 3 inputs – A and B inputs from 16-input multiplexers and a carry input from the LUT output of the previous CLU. The A and B input multiplexers can select port pins or the output of any CLU. Since there are many possible functions with 3 inputs, it can be quite challenging to determine the appropriate value to write to the LUT register (CLUnFN). The LUT implements combinatorial Boolean logic, and there is a way to programmatically determine the value to write to CLUnFN using combination Boolean functions. The examples discussed in this document use a header file SI_LUT.h that contains macros and definitions to simplify the LUT initialization. For example, if we wish to implement LUT logic such as: (A AND B) OR C The C code would be: CLU0FN = LUT_OR( LUT_AND(SI_LUT_A, SI_LUT_B), SI_LUT_C ) Alternatively, the look up table can be initialized using the Simplicity Studio Configurator. Each CLU contains a D flip-flop, whose input is the LUT output. The D flip-flop clock is selected using the CLKSEL bitfield in the CLUnCF register. The D flip-flop can be bypassed by using setting the OUTSEL bit high in the CLUnCN register. silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 1 AN921: Configurable Logic Unit SR Latch 2. SR Latch Configurable Logic Units can be used to build a SR latch. This section shows how this memory circuit can be built without using the D flip-flop portion of the CLU. This is advantageous in applications where we may want the output of the latch to be sent to another CLU via the carry input. 2.1 Background The truth table for an SR latch is shown below. When the inputs SET = RESET = 0, the next output (QNEXT) will remain the same as the current output (Q). When SET = 0, RESET = 1, the next output will be reset to 0. When SET = 1, RESET = 0, the next output will be set to 1. When SET = RESET = 1, the next output is not defined. Table 2.1. Truth Table of SR Latch (Simplified) SET RESET Q 00X 01X 10X 11X QNEXT Q 0 1 Undefined Comments Hold state Reset Set Undefined silabs.com | Smart. Connected. Energy-friendly. Rev. 0.1 | 2 AN921: Configurable Logic Unit SR Latch 2.2 SR Latch Implementation To implement the SR latch, signals SET, RESET and Q must be assigned to CLU inputs and outputs. SET can be assigned to CLU1's MXA input. The current output Q can be assigned to CLU1's MXB input. The last available input to CLU1 is the Carry, which always the output of the previous CLU. Therefore, RESET is assigned to CLU0's MXA, and the CLU0 LUT implements a buffer, as shown below. RESET CLU0 MXA CLU1 CARRY IN SET MXA 1 0 Figure 2.1. Block Diagram of SR Latch MXB Q The SR latch truth table can now be expanded as shown below. When the rows are ordered as shown, the QNEXT column read from top to bottom is the binary value, from most-significant bit to least-significant bit, written to the LUT register to implement the SR latch. Therefore, CLU1FN should be initialized to 0x74. Table 2.2. Truth Table of SR Latch (Expanded) SET (MXA) 1 1 1 1 0 0 0 0 Q (MXB) 1 1 0 0 1 1 0 0 RESET (CARRY IN) 1 0 1 0 1 0 1 0 QNEXT 0.


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