64/256/512/1K/2K/4K x 18 Synchronous FIFOs
CY7C4425/4205/4215 CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features
■ High speed, low power, firs...
Description
CY7C4425/4205/4215 CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features
■ High speed, low power, first-in first-out (FIFO) memories ■ 64 x 18 (CY7C4425) ■ 256 x 18 (CY7C4205) ■ 512 x 18 (CY7C4215) ■ 1K x 18 (CY7C4225) ■ 2K x 18 (CY7C4235) ■ 4K x 18 (CY7C4245) ■ High speed 100 MHz operation (10 ns read/write cycle time) ■ Low power (ICC = 45 mA) ■ Fully asynchronous and simultaneous read and write operation ■ Empty, Full, Half Full, and Programmable Almost Empty/Almost
Full status flags ■ TTL compatible ■ Retransmit function ■ Output Enable (OE) pin ■ Independent read and write enable pins ■ Center power and ground for reduced noise ■ Supports free running 50% duty cycle clock inputs ■ Width Expansion Capability ■ Depth Expansion Capability ■ Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC
Functional Description
The CY7C42X5 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK)...
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