X9271 Potentiometer Datasheet

X9271 Datasheet, PDF, Equivalent


Part Number

X9271

Description

Single Digitally Controlled Potentiometer

Manufacture

Intersil

Total Page 18 Pages
Datasheet
Download X9271 Datasheet


X9271
Data Sheet
X9271
Single Supply/Low Power/256-Tap/SPI Bus
July 18, 2014
FN8174.4
Single, Digitally Controlled (XDCP™)
Potentiometer
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can
be directly written to and read by the user. The contents of
the WCR control the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• 256 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical at VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position on
Power-up
• Standby Current <3µA Max
• VCC = 2.7V to 5.5V Operation
• 50kΩ End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
VCC
SPI
BUS
INTERFACE
ADDRESS
DATA
STATUS
WRITE
READ
TRANSFER
INC/DEC
BUS
INTERFACE
AND CONTROL
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
16 Bytes
RH
50kΩ
256 TAPS
POT
VSS
RW RL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2011, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

X9271
X9271
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
VCC LIMITS POTENTIOMETER TEMP. RANGE
MARKING
(V) ORGANIZATION (kΩ)
(°C)
PACKAGE
Pb-Free
PKG.
DWG. #
X9271UV14IZ (Note 1)
X9271 UVZI 5 ±10%
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z (Note 1)
X9271 UVZ
5 ±10%
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7
X9271 UVZG 2.7 to 5.5
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14IZ-2.7T1
X9271 UVZG 2.7 to 5.5
50
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7
X9271 UVZF 2.7 to 5.5
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
X9271UV14Z-2.7T1
X9271 UVZF 2.7 to 5.5
50
0 to +70 14 Ld TSSOP (4.4mm)
M14.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
Pin Configuration
X9271
14 LD TSSOP
TOP VIEW
S0
A0
NC
CS
SCK
SI
VSS
1
2
3
4
5
6
7
14 VCC
13 RL
12 RH
11 RW
10 HOLD
9 A1
8 WP
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN NAME
SO
A0
NC
CS
SCK
SI
VSS
WP
A1
HOLD
RW
RH
RL
VCC
Serial Data Output
Device Address
No Connect
Chip Select
Serial Clock
Serial Data Input
System Ground
Hardware Write Protect
Device Address
Device Select. Pause the serial bus.
Wiper Terminal of Potentiometer
High Terminal of Potentiometer
Low Terminal of Potentiometer
System Supply Voltage
FUNCTION
Submit Document Feedback
2
FN8174.4
July 18, 2014


Features Data Sheet X9271 Single Supply/Low Powe r/256-Tap/SPI Bus July 18, 2014 FN817 4.4 Single, Digitally Controlled (XDCP ™) Potentiometer The X9271 integrates a single, digitally controlled potenti ometer (XDCP™) on a monolithic CMOS i ntegrated circuit. The digitally contro lled potentiometer is implemented by us ing 255 resistive elements in a series array. Between each element are tap poi nts connected to the wiper terminal thr ough switches. The position of the wipe r on the array is controlled by the use r through the SPI bus interface. The po tentiometer has associated with it a vo latile Wiper Counter Register (WCR) and four nonvolatile data registers that c an be directly written to and read by t he user. The contents of the WCR contro l the position of the wiper on the resi stor array though the switches. Power-u p recalls the contents of the default d ata register (DR0) to the WCR. The XDCP can be used as a three-terminal potent iometer or as a two-terminal variable resistor in a wide variety of.
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