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Data Sheet
Microwave Wideband Synthesizer with Integrated VCO ADF5355
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 13,600 MHz Fractional-N synthesizer and integer-N synthesizer High resolution 38-bit modulus Phase frequency detector (PFD) operation to 125 MHz Reference frequency operation to 600 MHz Maintains frequency lock over −40°C to +85°C Low phase noise, voltage controlled oscillator (VCO) Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output Analog and digital power supplies: 3.3 V Charge pump and VCO power supplies: 5.0 V, typical Logic compatibility: 1.8 V Programmable dual modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function Analog and digital lock detect Supported in the ADIsimPLL design tool
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation
The ADF5355 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 54 MHz to 6800 MHz.
The ADF5355 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.
Control of all on-chip registers is through a simple 3-wire interface. The ADF5355 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF5355 also contains hardware and software power-down modes.
CE AVDD
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP RSET VVCO
VRF
REFINA REFIN B
CLK DATA
LE
×2 DOUBLER
10-BIT R COUNTER
÷2 DIVIDER
DATA REGISTER
FUNCTION LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER FRACTIONAL INTERPOLATOR
N COUNTER
LOCK DETECT
MULTIPLEXER
CHARGE PUMP
PHASE COMPARATOR
VCO CORE
×2
÷ 1/2/4/8/ 16/32/64
MUXOUT CREG1 CREG2
CPOUT
OUTPUT STAGE
OUTPUT STAGE
VTUNE VREF VBIAS
VREGVCO
RFOUTB
PDBRF RFOUTA+ RFOUTA–
MULTIPLEXER
ADF5355
12714-001
AGND
CPGND
AGNDRF
Figure 1.
SDGND AGNDVCO
4
Rev. D
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ADF5355
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4
Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 8
Transistor Count........................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Circuit Description......................................................................... 16 Reference Input........................................................................... 16 RF N Divider............................................................................... 16 Phase Frequency Detector (PFD) and Charge Pump............ 17 MUXOUT and Lock Detect...................................................... 17 Input Shift Registers ................................................................... 17 Program Modes ............................