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SI5347 Dataheets PDF



Part Number SI5347
Manufacturers Silicon Laboratories
Logo Silicon Laboratories
Description ANY-OUTPUT JITTER ATTENUATORS
Datasheet SI5347 DatasheetSI5347 Datasheet (PDF)

Si5347/46 D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS Si5347C/D Features  Four or two independent DSPLLs in a  Automatic free-run and holdover modes single monolithic IC  Fastlock feature for low nominal  Each DSPLL generates any output bandwidths frequency from any input frequency  Input frequency range:  Glitchless on-the-fly DSPLL frequency changes Differential: 8 kHz to 750 MHz  DCO mode: as low as 0.01 ppb steps LVCMOS: 8 kHz to 250 MH.

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Si5347/46 D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS Si5347C/D Features  Four or two independent DSPLLs in a  Automatic free-run and holdover modes single monolithic IC  Fastlock feature for low nominal  Each DSPLL generates any output bandwidths frequency from any input frequency  Input frequency range:  Glitchless on-the-fly DSPLL frequency changes Differential: 8 kHz to 750 MHz  DCO mode: as low as 0.01 ppb steps LVCMOS: 8 kHz to 250 MHz  Output frequency range: per DSPLL  Core voltage: Differential: up to 712.5 MHz VDD: 1.8 V ±5% LVCMOS: up to 250 MHz  Ultra low jitter: VDDA: 3.3 V ±5%  Independent output clock supply pins: <100 fs typ (12 kHz–20 MHz) 3.3, 2.5, or 1.8 V  Flexible crosspoints route any input to  Output-output skew: any output clock <20 ps (typ) per DSPLL   Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz programming range Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML,    Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilderTM Pro software tool and HCSL with programmable signal simplifies device configuration amplitude  Si5347: Quad DSPLL, 4 input,  Status monitoring (LOS, OOF, LOL) 4 or 8 output, 64 QFN  Hitless input clock switching: automatic  Si5346: Dual DSPLL, 4 input, or manual  Locks to gapped clock inputs 4 output, 44 QFN  Temperature range: –40 to +85 °C  Pb-free, RoHS-6 compliant Device Selector Guide Grade Si5347A Si5347C Si5346A Si5347B Si5347D Si5346B PLLs/OUTs 4/8 4/4 2/4 4/8 4/4 2/4 Max Output Freq 712.5 MHz 712.5 MHz 712.5 MHz 350 MHz 350 MHz 350 MHz Frequency Synthesis Modes Integer + Fractional Integer + Fractional Integer + Fractional Integer + Fractional Integer + Fractional Integer + Fractional Applications 9x9 mm 7x7 mm Ordering Information: See section 8 Functional Block Diagram XTAL/ REFCLK Si5347 XA XB OSC IN0 ÷FRAC IN1 ÷FRAC IN2 ÷FRAC IN3 ÷FRAC NVM I2C/SPI Control/ Status DSPLL A DSPLL B DSPLL C DSPLL D ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7  OTN Muxponders and Transponders  10/40/100G network line cards  GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)  Carrier Ethernet switches  Broadcast video Description The Si5347 is a high performance jitter attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347/46 is pro.


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