SI5380

Ultra-Low Phase Noise, 12-output JESD204B Clock Generator Si5380 Data Sheet The Si5380 is a high performance, integer-based (M/N) clock generator for small cell applications which demand the highest level of integration and phase noise performance. Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5380 combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Applications JESD204B clock generation Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) Remote Radio Head (RRH), wireless repeaters, wireless backhaul Data conversion sampling clocks (ADC, DAC, DDC, DUC) KEY FEATURES Digital frequency synthesis eliminates external VCXO and analog loop filter components Supports JESD204B clocking: DCLK and SYSREF Input frequency range: Differential: 10 MHz – 750 MHz LVCMOS: 10 MHz – 250 MHz Output frequency range: Differential: 480 kHz – 1.47456 GHz LVCMOS: 480 kHz – 250 MHz IN_SEL IN0 IN1 IN2 IN3/ FB_IN ÷P0 ÷P1 ÷P2 ÷P3 I2C_SEL SDA/SDI A1/SDO SCLK A0/CSb I2C/ SPI NVM INTRb LOLb Status Monitor PDNb RSTb 54MHz XTAL X...