Clock Generator. SI5380 Datasheet

SI5380 Generator. Datasheet pdf. Equivalent

Part SI5380
Description Clock Generator
Feature Ultra-Low Phase Noise, 12-output JESD204B Clock Generator Si5380 Data Sheet The Si5380 is a high pe.
Manufacture Silicon Laboratories
Datasheet
Download SI5380 Datasheet




SI5380
Ultra-Low Phase Noise, 12-output JESD204B
Clock Generator
Si5380 Data Sheet
The Si5380 is a high performance, integer-based (M/N) clock generator for small cell ap-
plications which demand the highest level of integration and phase noise performance.
Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5380 combines
frequency synthesis and jitter attenuation in a highly integrated digital solution that elimi-
nates the need for external VCXO and loop filter components. A low cost, fixed-frequen-
cy crystal provides frequency stability for free-run and holdover modes. This all-digital
solution provides superior performance that is highly immune to external board distur-
bances such as power supply noise.
Applications
• JESD204B clock generation
• Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells
• Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A)
• Remote Radio Head (RRH), wireless repeaters, wireless backhaul
• Data conversion sampling clocks (ADC, DAC, DDC, DUC)
KEY FEATURES
• Digital frequency synthesis eliminates
external VCXO and analog loop filter
components
• Supports JESD204B clocking: DCLK and
SYSREF
• Input frequency range:
• Differential: 10 MHz – 750 MHz
• LVCMOS: 10 MHz – 250 MHz
• Output frequency range:
• Differential: 480 kHz – 1.47456 GHz
• LVCMOS: 480 kHz – 250 MHz
IN_SEL
IN0
IN1
IN2
IN3/
FB_IN
÷P0
÷P1
÷P2
÷P3
I2C_SEL
SDA/SDI
A1/SDO
SCLK
A0/CSb
I2C/
SPI
NVM
INTRb
LOLb
Status
Monitor
PDNb RSTb
54MHz
XTAL
XA XB Si5380
OSC
÷R0A
OUT0A
DSPLL
÷R0 OUT0
÷R1 OUT1
÷R2 OUT2
÷N0 t0
÷N1 t1
÷N2 t2
÷N3 t3
÷N4 t4
÷R3 OUT3
÷R4 OUT4
÷R5 OUT5
÷R6 OUT6
÷R7 OUT7
÷R8 OUT8
÷R9 OUT9
÷R9A
OUT9A
SYNCb OEb
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.96



SI5380
1. Feature List
The Si5380 highlighted features are listed below.
• Digital frequency synthesis eliminates external VCXO and an-
alog loop filter components
• Supports JESD204B clocking: DCLK and SYSREF
• Input frequency range:
• Differential: 10 MHz – 750 MHz
• LVCMOS: 10 MHz – 250 MHz
• Output frequency range:
• Differential: up to 1.47456 GHz
• LVCMOS: up to 250 MHz
• Excellent jitter performance:
• 70 fs typ (12 kHz – 20 MHz)
• Phase noise floor: –159 dBc/Hz
• Spur performance: –103 dBc max (relative to a 122.88 MHz
carrier)
• Configurable outputs:
• Signal swing: 200 to 3200 mVpp
• Compatible with LVDS, LVPECL
• LVCMOS 3.3, 2.5, or 1.8 V
• Output-output skew: 20 ps (typical, same N-divider)
• Adjustable output-output delay: 68 ps/step, ±128 steps
Si5380 Data Sheet
Feature List
• Optional Zero Delay mode
• Independent output supply pins: 3.3, 2.5, or 1.8 V
• Core voltage:
• VDD = 1.8 V ±5%
• VDDA = 3.3 V ±5%
• Automatic free-run, lock, and holdover modes
• Digitally selectable loop bandwidth: 0.1 Hz to 4 kHz
• Hitless input clock switching
• Status monitoring (LOS, OOF, LOL)
• Serial interface: I2C or SPI In-circuit programmable with non-
volatile OTP memory
ClockBuilderTM Pro software tool simplifies device configura-
tion
• 4 input, 12 output, 64QFN
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.96 | 1







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