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shift register. NPIC6C595 Datasheet

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shift register. NPIC6C595 Datasheet






NPIC6C595 register. Datasheet pdf. Equivalent




NPIC6C595 register. Datasheet pdf. Equivalent





Part

NPIC6C595

Description

Power logic 8-bit shift register



Feature


NPIC6C595 Power logic 8-bit shift regis ter; open-drain outputs Rev. 1 — 20 August 2012 Product data sheet 1. Gen eral description The NPIC6C595 is an 8- bit serial-in/serial or parallel-out sh ift register with a storage register an d open-drain outputs. Both the shift an d storage register have separate clocks . The device features a serial input (D S) and a serial outp.
Manufacture

NXP

Datasheet
Download NPIC6C595 Datasheet


NXP NPIC6C595

NPIC6C595; ut (Q7S) to enable cascading and an asyn chronous reset input (MR). A LOW on MR resets both the shift register and stor age register. Data is shifted on the LO W-to-HIGH transitions of the SHCP input . The data in the shift register is tra nsferred to the storage register on a L OW-to-HIGH transition of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the.


NXP NPIC6C595

SHCP input. If both clocks are connecte d together, the shift register is alway s one clock pulse ahead of the storage register. Data in the storage register drives the gate of the output extended- drain NMOS transistor whenever the outp ut enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high- impedance OFF-state. Operation of the O E input does not a.


NXP NPIC6C595

ffect the state of the registers. The op en-drain outputs are 33 V/100 mA contin uous current extended-drain NMOS transi stors designed for use in systems that require moderate load power such as LED s. Integrated voltage clamps in the out puts provide protection against inducti ve transients. This feature makes the d evice suitable for power driver applica tions such as rela.

Part

NPIC6C595

Description

Power logic 8-bit shift register



Feature


NPIC6C595 Power logic 8-bit shift regis ter; open-drain outputs Rev. 1 — 20 August 2012 Product data sheet 1. Gen eral description The NPIC6C595 is an 8- bit serial-in/serial or parallel-out sh ift register with a storage register an d open-drain outputs. Both the shift an d storage register have separate clocks . The device features a serial input (D S) and a serial outp.
Manufacture

NXP

Datasheet
Download NPIC6C595 Datasheet




 NPIC6C595
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 20 August 2012
Product data sheet
1. General description
The NPIC6C595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset input (MR). A LOW on MR resets both the shift register and
storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The
data in the shift register is transferred to the storage register on a LOW-to-HIGH transition
of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the SHCP input.
If both clocks are connected together, the shift register is always one clock pulse ahead of
the storage register. Data in the storage register drives the gate of the output
extended-drain NMOS transistor whenever the output enable input (OE) is LOW. A HIGH
on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE
input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA
continuous current extended-drain NMOS transistors designed for use in systems that
require moderate load power such as LEDs. Integrated voltage clamps in the outputs
provide protection against inductive transients. This feature makes the device suitable for
power driver applications such as relay, solenoids and other low-current or
medium-voltage loads.
2. Features and benefits
Specified from 40 C to +125 C
Low RDSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
All registers cleared with single input
Low power consumption
ESD protection:
HBM JDS-001 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V
3. Applications
LED sign
Graphic status panel
Fault status indicator




 NPIC6C595
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
NPIC6C595D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
NPIC6C595PW
40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
NPIC6C595BQ
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
5. Functional diagram
15 10
SHCP
STCP
Q0
3
Q1 4
5
Q2
2
DS
6
Q3
Q4 11
Q5 12
13
Q6
14
Q7
Q7S 9
MR OE
78
aaa-002547
Fig 1. Logic symbol
VCC
2 DS
15 SHCP
7 MR
8-STAGE SHIFT REGISTER
10 STCP
8-BIT STORAGE REGISTER
Q7S 9
8 OE
OPEN-DRAIN OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
3 4 5 6 11 12 13 14
aaa-002542
Fig 2. Functional diagram
Qn
33 V
GND
Fig 3. Schematic of all inputs
aaa-002550
GND
aaa-002551
Fig 4. Schematic of open-drain outputs (Qn)
NPIC6C595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 August 2012
© NXP B.V. 2012. All rights reserved.
2 of 20




 NPIC6C595
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
DS
SHCP
MR
STCP
OE
STAGE 0
DQ
LATCH
0
CP
R
STAGE 1 TO 6
DQ
STAGE 7
DQ
LATCH
7
CP
R
R
DQ
LATCH
CP
R
DQ
LATCH
CP
Q7S
GND
Fig 5. Logic diagram
GND
Q0 Q1 Q2 Q3 Q4 Q5 Q6
aaa-002543
Q7
SHCP
OE
DS
STCP
MR
Q1
76543210
Fig 6. Timing diagram
5V
GND
5V
GND
5V
GND
5V
GND
5V
GND
VOH
VOL
aaa-002553
NPIC6C595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 August 2012
© NXP B.V. 2012. All rights reserved.
3 of 20






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