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CLOCK GENERATOR. SI52112-A1 Datasheet

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CLOCK GENERATOR. SI52112-A1 Datasheet






SI52112-A1 GENERATOR. Datasheet pdf. Equivalent




SI52112-A1 GENERATOR. Datasheet pdf. Equivalent





Part

SI52112-A1

Description

PCI-EXPRESS GEN 1 DUAL OUTPUT CLOCK GENERATOR



Feature


Si52112-A1/A2 PCI-EXPRESS GEN 1 DUAL OU TPUT CLOCK GENERATOR Features  PCI -Express Gen 1 compliant  3.3 V Powe r supply  Low power HCSL differenti al output buffers  Small package 10 -pin TDFN (3x3 mm)  Supports Serial -ATA (SATA) at  Si52112-A1 does not support 100 MHz spread spectrum outpu ts  No termination resistors requir ed  Si52112-A2 supports 0.5% do.
Manufacture

Silicon Laboratories

Datasheet
Download SI52112-A1 Datasheet


Silicon Laboratories SI52112-A1

SI52112-A1; wn  25 MHz Crystal Input or Clock s pread outputs input  For PCIe Gen 2 applications, see  Triangular spr ead spectrum Si52112-B3/B4 profile fo r maximum EMI  For PCIe Gen 3 appli cations, see reduction (Si52112-A2) S i52112-B5/B6  Extended Temperature: –40 to 85 °C Applications  Net work Attached Storage  Multi-functio n Printer  Wireless Access Point .


Silicon Laboratories SI52112-A1

 Routers Description Si52112-A1/A2 i s a high-performance, PCIe clock genera tor that can source two PCIe clocks fro m a 25 MHz crystal or clock input. The clock outputs are compliant to PCIe Gen 1 specifications. The ultra-small foot print (3x3 mm) and industry leading low power consumption make Si52112-A1/A2 t he ideal clock solution for consumer an d embedded applicati.


Silicon Laboratories SI52112-A1

ons. Ordering Information: See page 13 Pin Assignments VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 DIFF2 8 DIFF2 7 DIFF1 6 DIFF1 Patents pending VDD XIN/CLKIN XOUT PLL Divider DIFF1 DIFF 2 VSS Rev 1.2 7/14 Copyright © 2014 by Silicon Laboratories Si52112-A1/A2 Si52112-A1/A2 2 Rev 1.2 TABLE OF CON TENTS Si52112-A1/A2 Section Page 1. Electrical Specifi.

Part

SI52112-A1

Description

PCI-EXPRESS GEN 1 DUAL OUTPUT CLOCK GENERATOR



Feature


Si52112-A1/A2 PCI-EXPRESS GEN 1 DUAL OU TPUT CLOCK GENERATOR Features  PCI -Express Gen 1 compliant  3.3 V Powe r supply  Low power HCSL differenti al output buffers  Small package 10 -pin TDFN (3x3 mm)  Supports Serial -ATA (SATA) at  Si52112-A1 does not support 100 MHz spread spectrum outpu ts  No termination resistors requir ed  Si52112-A2 supports 0.5% do.
Manufacture

Silicon Laboratories

Datasheet
Download SI52112-A1 Datasheet




 SI52112-A1
Si52112-A1/A2
PCI-EXPRESS GEN 1 DUAL OUTPUT CLOCK GENERATOR
Features
PCI-Express Gen 1 compliant 3.3 V Power supply
Low power HCSL differential
output buffers
Small package 10-pin TDFN
(3x3 mm)
Supports Serial-ATA (SATA) at Si52112-A1 does not support
100 MHz
spread spectrum outputs
No termination resistors required Si52112-A2 supports 0.5% down
25 MHz Crystal Input or Clock
spread outputs
input
For PCIe Gen 2 applications, see
Triangular spread spectrum
Si52112-B3/B4
profile for maximum EMI
For PCIe Gen 3 applications, see
reduction (Si52112-A2)
Si52112-B5/B6
Extended Temperature:
–40 to 85 °C
Applications
Network Attached Storage
Multi-function Printer
Wireless Access Point
Routers
Description
Si52112-A1/A2 is a high-performance, PCIe clock generator that can
source two PCIe clocks from a 25 MHz crystal or clock input. The clock
outputs are compliant to PCIe Gen 1 specifications. The ultra-small
footprint (3x3 mm) and industry leading low power consumption make
Si52112-A1/A2 the ideal clock solution for consumer and embedded
applications.
Ordering Information:
See page 13
Pin Assignments
VDD 1
XOUT 2
XIN/CLKIN 3
VSS 4
VSS 5
10 VDD
9 DIFF2
8 DIFF2
7 DIFF1
6 DIFF1
Patents pending
VDD
XIN/CLKIN
XOUT
PLL Divider
DIFF1
DIFF2
VSS
Rev 1.2 7/14
Copyright © 2014 by Silicon Laboratories
Si52112-A1/A2




 SI52112-A1
Si52112-A1/A2
2 Rev 1.2




 SI52112-A1
TABLE OF CONTENTS
Si52112-A1/A2
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. 10-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev 1.2
3



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