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CLOCK BUFFER. SI53102-A2 Datasheet

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CLOCK BUFFER. SI53102-A2 Datasheet






SI53102-A2 BUFFER. Datasheet pdf. Equivalent




SI53102-A2 BUFFER. Datasheet pdf. Equivalent





Part

SI53102-A2

Description

FAN-OUT CLOCK BUFFER



Feature


Si53102-A1/A2/A3 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER Features  PCI-Express Gen 1 , Gen 2,  2.5 V or 3.3 V Power supp ly Gen 3, and Gen 4 common clock  S pread Spectrum Tolerant compliant  Extended Temperature:  Two low-pow er PCIe clock –40 to 85 °C outputs  Small package 8-pin TDFN  Sup ports Serial-ATA (SATA) at (1.4x1.6.
Manufacture

Silicon Laboratories

Datasheet
Download SI53102-A2 Datasheet


Silicon Laboratories SI53102-A2

SI53102-A2; mm) 100 MHz  For PCIe Gen 1: Si531 02-A1  No termination resistors req uired for differential clocks  For PCIe Gen 2: Si53102-A2  For PCIe G en 3/4: Si53102-A3 Applications  Ne twork Attached Storage  Multi-functi on Printer  Wireless Access Point Server/Storage Ordering Information : See page 11 Pin Assignments Descript ion Si53102-A1/A2/A3 is a family o.


Silicon Laboratories SI53102-A2

f high-performance 1:2 PCIe fan output b uffers. This low-additive-jitter clock buffer family is compliant to PCIe Gen 1, Gen 2, Gen 3, and Gen 4 specificatio ns. The ultra-small footprint (1.4x1.6 mm) and industry-leading low power cons umption make the Si53102-A1/A2/A3 the i deal clock solution for consumer and em bedded applications. Measuring PCIe clo ck jitter is quick.


Silicon Laboratories SI53102-A2

and easy with the Silicon Labs PCIe Clo ck Jitter Tool. Download it for free at www.silabs.com/pcielearningcenter. Fun ctional Block Diagram DIFFIN 1 DIFFIN 2 DIFF1 3 DIFF1 4 Patents pending 8 VD D 7 DIFF2 6 DIFF2 5 VSS VDD DIFFIN DI FFIN DIFF1 DIFF2 VSS Rev 1.2 12/15 Copyright © 2015 by Silicon Laboratori es Si53102-A1/A2/A3 Si53102-A1/A2/A3 2 Rev 1.2 TABLE OF.

Part

SI53102-A2

Description

FAN-OUT CLOCK BUFFER



Feature


Si53102-A1/A2/A3 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER Features  PCI-Express Gen 1 , Gen 2,  2.5 V or 3.3 V Power supp ly Gen 3, and Gen 4 common clock  S pread Spectrum Tolerant compliant  Extended Temperature:  Two low-pow er PCIe clock –40 to 85 °C outputs  Small package 8-pin TDFN  Sup ports Serial-ATA (SATA) at (1.4x1.6.
Manufacture

Silicon Laboratories

Datasheet
Download SI53102-A2 Datasheet




 SI53102-A2
Si53102-A1/A2/A3
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2
FAN-OUT CLOCK BUFFER
Features
PCI-Express Gen 1, Gen 2,
2.5 V or 3.3 V Power supply
Gen 3, and Gen 4 common clock Spread Spectrum Tolerant
compliant
Extended Temperature:
Two low-power PCIe clock
–40 to 85 °C
outputs
Small package 8-pin TDFN
Supports Serial-ATA (SATA) at (1.4x1.6 mm)
100 MHz
For PCIe Gen 1: Si53102-A1
No termination resistors required
for differential clocks
For PCIe Gen 2: Si53102-A2
For PCIe Gen 3/4: Si53102-A3
Applications
Network Attached Storage
Multi-function Printer
Wireless Access Point
Server/Storage
Ordering Information:
See page 11
Pin Assignments
Description
Si53102-A1/A2/A3 is a family of high-performance 1:2 PCIe fan output
buffers. This low-additive-jitter clock buffer family is compliant to PCIe
Gen 1, Gen 2, Gen 3, and Gen 4 specifications. The ultra-small footprint
(1.4x1.6 mm) and industry-leading low power consumption make the
Si53102-A1/A2/A3 the ideal clock solution for consumer and embedded
applications. Measuring PCIe clock jitter is quick and easy with the Silicon
Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-
learningcenter.
Functional Block Diagram
DIFFIN 1
DIFFIN 2
DIFF1 3
DIFF1 4
Patents pending
8 VDD
7 DIFF2
6 DIFF2
5 VSS
VDD
DIFFIN
DIFFIN
DIFF1
DIFF2
VSS
Rev 1.2 12/15
Copyright © 2015 by Silicon Laboratories
Si53102-A1/A2/A3




 SI53102-A2
Si53102-A1/A2/A3
2 Rev 1.2




 SI53102-A2
TABLE OF CONTENTS
Si53102-A1/A2/A3
Table of Contents
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Rev 1.2
3



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