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3 BUFFER. SI53112 Datasheet

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3 BUFFER. SI53112 Datasheet






SI53112 BUFFER. Datasheet pdf. Equivalent




SI53112 BUFFER. Datasheet pdf. Equivalent





Part

SI53112

Description

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER



Feature


Si53112 DB1200ZL 12-OUTPUT PCIE GEN 3 B UFFER Features  Twelve 0.7 V low-p ower, push-  PLL or bypass mode pul l, HCSL-compatible  Spread spectrum tolerable PCIe Gen 3 outputs  1.0 5 to 3.3 V I/O supply voltage   Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, s upports PCIe and QPI    50 p s output-to-output skew 50 ps cyc-cy.
Manufacture

Silicon Laboratories

Datasheet
Download SI53112 Datasheet


Silicon Laboratories SI53112

SI53112; c jitter (PLL mode) Low phase jitter (In tel QPI, PCIe Gen 1/2/3/4 common clock compliant)  PLL bandwidth SW SMBUS programming overrides the latch  Gen 3 SRNS Compliant value from HW pin  100 ps input-to-output delay   9 selectable SMBUS addresses SMBu s address configurable to allow multipl e buffers in a single   Extende d Temperature: –40 to 85 °C Pack.


Silicon Laboratories SI53112

age: 64-pin QFN control network 3.3 V s upply  For higher output devices or voltage operation variations of this device, contact Silicon Labs Ordering Information: See page 30. Patents pend ing Applications  Server  Storag e  Datacenter  Enterprise Switch es and Routers Description The Si53112 is a low-power, 12-output, differentia l clock buffer that meets al.


Silicon Laboratories SI53112

l of the performance requirements of the Intel DB1200ZL specification. The devi ce is optimized for distributing refere nce clocks for Intel® QuickPath Interc onnect (Intel QPI), PCIe Gen 1/Gen 2/Ge n 3/Gen 4, SAS, SATA, and Intel Scalabl e Memory Interconnect (Intel SMI) appli cations. The VCO of the device is optim ized to support 100 MHz and 133 MHz ope ration. Each differ.

Part

SI53112

Description

DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER



Feature


Si53112 DB1200ZL 12-OUTPUT PCIE GEN 3 B UFFER Features  Twelve 0.7 V low-p ower, push-  PLL or bypass mode pul l, HCSL-compatible  Spread spectrum tolerable PCIe Gen 3 outputs  1.0 5 to 3.3 V I/O supply voltage   Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, s upports PCIe and QPI    50 p s output-to-output skew 50 ps cyc-cy.
Manufacture

Silicon Laboratories

Datasheet
Download SI53112 Datasheet




 SI53112
Si53112
DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER
Features
Twelve 0.7 V low-power, push- PLL or bypass mode
pull, HCSL-compatible
Spread spectrum tolerable
PCIe Gen 3 outputs
1.05 to 3.3 V I/O supply voltage
Individual OE HW pins for each
output clock
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)
PLL bandwidth SW SMBUS
programming overrides the latch
Gen 3 SRNS Compliant
value from HW pin
100 ps input-to-output delay
9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single
Extended Temperature:
–40 to 85 °C
Package: 64-pin QFN
control network 3.3 V supply For higher output devices or
voltage operation
variations of this device, contact
Silicon Labs
Ordering Information:
See page 30.
Patents pending
Applications
Server
Storage
Datacenter
Enterprise Switches and Routers
Description
The Si53112 is a low-power, 12-output, differential clock buffer that meets
all of the performance requirements of the Intel DB1200ZL specification.
The device is optimized for distributing reference clocks for Intel®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53112




 SI53112
Si53112
Functional Block Diagram
OE_[11:0]
12
CLK_IN
CLK_IN
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
SSC Compatible
PLL
Control
Logic
FB_OUT
DIF_[11:0]
2 Rev. 1.1




 SI53112
TABLE OF CONTENTS
Si53112
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. OE and Output Enables (Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5. PWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8. Buffer Power-Up State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Pin Descriptions: 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Rev. 1.1
3



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