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FANOUT BUFFER. SI53152 Datasheet

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FANOUT BUFFER. SI53152 Datasheet






SI53152 BUFFER. Datasheet pdf. Equivalent




SI53152 BUFFER. Datasheet pdf. Equivalent





Part

SI53152

Description

FANOUT BUFFER



Feature


Si53152 PCI-EXPRESS GEN 1, GEN 2, GEN 3 , AND GEN 4 FANOUT BUFFER Features PCI-Express Gen 1, Gen 2, Gen 3,  Dedicated output enable pin for and Ge n 4 common clock each clock compliant  Two PCI-Express buffered clock Supports Serial ATA (SATA) at outpu ts 100 MHz  Supports LVDS outputs  100–210 MHz operation  I2C s upport with readback  Low power,.
Manufacture

Silicon Laboratories

Datasheet
Download SI53152 Datasheet


Silicon Laboratories SI53152

SI53152; push pull, differential capabilities output buffers  Extended temperatur e:  Internal termination for maximu m –40 to 85 oC integration  3.3 V Power supply  24-pin QFN package Applications Ordering Information: S ee page 17  Network attached storag e  Multi-function Printer  Wirel ess access point  Routers Pin Assig nments VSS DIFFIN DIFFIN VDD SDATA .


Silicon Laboratories SI53152

SCLK Description The Si53152 is a sprea d spectrum tolerant PCIe clock buffer t hat can source two PCIe clocks simultan eously. The device has two hardware out put enable inputs for enabling the resp ective differential outputs on the fly. The device also features output enable control through I2C communication. I2C programmability is also available to d ynamically control.


Silicon Laboratories SI53152

skew, edge rate and amplitude on the tr ue, compliment, or both differential si gnals on the clock outputs. This contro l feature enables optimal signal integr ity as well as optimal EMI signature on the clock outputs. Measuring PCIe cloc k jitter is quick and easy with the Sil icon Labs PCIe Clock Jitter Tool. Downl oad it for free at www.silabs.com/pcie- learningcenter. V.

Part

SI53152

Description

FANOUT BUFFER



Feature


Si53152 PCI-EXPRESS GEN 1, GEN 2, GEN 3 , AND GEN 4 FANOUT BUFFER Features PCI-Express Gen 1, Gen 2, Gen 3,  Dedicated output enable pin for and Ge n 4 common clock each clock compliant  Two PCI-Express buffered clock Supports Serial ATA (SATA) at outpu ts 100 MHz  Supports LVDS outputs  100–210 MHz operation  I2C s upport with readback  Low power,.
Manufacture

Silicon Laboratories

Datasheet
Download SI53152 Datasheet




 SI53152
Si53152
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4
FANOUT BUFFER
Features
PCI-Express Gen 1, Gen 2, Gen 3, Dedicated output enable pin for
and Gen 4 common clock
each clock
compliant
Two PCI-Express buffered clock
Supports Serial ATA (SATA) at
outputs
100 MHz
Supports LVDS outputs
100–210 MHz operation
I2C support with readback
Low power, push pull, differential
capabilities
output buffers
Extended temperature:
Internal termination for maximum
–40 to 85 oC
integration
3.3 V Power supply
24-pin QFN package
Applications
Ordering Information:
See page 17
Network attached storage
Multi-function Printer
Wireless access point
Routers
Pin Assignments
Description
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source
two PCIe clocks simultaneously. The device has two hardware output enable
inputs for enabling the respective differential outputs on the fly. The device
also features output enable control through I2C communication. I2C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
VDD 1
NC 2
VDD 3
VSS 4
OE_DIFF0* 5
VDD 6
24 23 22 21 20 19
18 OE_DIFF1*
17 VDD
25
GND
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
7 8 9 10 11 12
*Note: Internal 100 kohm pull-up.
Patents pending
Functional Block Diagram
DIFFIN
DIFFIN
SCLK
SDATA
OE [1:0]
Control & Memory
Control RAM
DIFF0
DIFF1
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53152




 SI53152
Si53152
2 Rev. 1.1




 SI53152
TABLE OF CONTENTS
Si53152
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Rev. 1.1
3



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