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FANOUT BUFFER. SI53159 Datasheet

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FANOUT BUFFER. SI53159 Datasheet






SI53159 BUFFER. Datasheet pdf. Equivalent




SI53159 BUFFER. Datasheet pdf. Equivalent





Part

SI53159

Description

FANOUT BUFFER



Feature


Si53159 PCI-EXPRESS GEN 1, GEN 2, GEN 3 , AND GEN 4 NINE OUTPUT FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2,  Up to nine buffered clocks Gen 3 , and Gen 4 common clock  100 to 210 MHz clock input range    co mpliant  Supports Serial-ATA (SATA ) at 100 MHz  Low power push-pull differential output buffers  No t ermination resistors required I2C s.
Manufacture

Silicon Laboratories

Datasheet
Download SI53159 Datasheet


Silicon Laboratories SI53159

SI53159; upport with readback capabilities Suppor ts spread spectrum input Extended tempe rature: –40 to 85 oC  Output enab le pins for all  3.3 V power supply buffered clocks  48-pin QFN packa ge Applications  Network attached s torage  Multi-function printers  Wireless access point  Servers Des cription The Si53159 is a high-performa nce, low additive jitter, PCIe clo.


Silicon Laboratories SI53159

ck buffer that can fan out nine PCIe clo cks. The clock outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, and Gen 4 sp ecifications. The device has six hardwa re output enable control pins for enabl ing and disabling differential outputs. The small footprint and low power cons umption makes the Si53159 the ideal clo ck solution for consumer and embedded a pplications. Measu.


Silicon Laboratories SI53159

ring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitte r Tool. Download it for free at www.sil abs.com/pcielearningcenter. Functional Block Diagram Ordering Information: S ee page 18. Pin Assignments NC NC VSS_ DIFF VSS_CORE NC NC DIFFIN DIFFIN VDD_C ORE CKPWRGD/PDB1 SDATA SCLK 48 47 46 4 5 44 43 42 41 40 39 38 37 VDD_DIFF 1 36 DIFF8 VDD_DIFF.

Part

SI53159

Description

FANOUT BUFFER



Feature


Si53159 PCI-EXPRESS GEN 1, GEN 2, GEN 3 , AND GEN 4 NINE OUTPUT FANOUT BUFFER Features  PCI-Express Gen 1, Gen 2,  Up to nine buffered clocks Gen 3 , and Gen 4 common clock  100 to 210 MHz clock input range    co mpliant  Supports Serial-ATA (SATA ) at 100 MHz  Low power push-pull differential output buffers  No t ermination resistors required I2C s.
Manufacture

Silicon Laboratories

Datasheet
Download SI53159 Datasheet




 SI53159
Si53159
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 NINE
OUTPUT FANOUT BUFFER
Features
PCI-Express Gen 1, Gen 2,
Up to nine buffered clocks
Gen 3, and Gen 4 common clock 100 to 210 MHz clock input range
compliant
Supports Serial-ATA (SATA) at
100 MHz
Low power push-pull differential
output buffers
No termination resistors required
I2C support with readback
capabilities
Supports spread spectrum input
Extended temperature:
–40 to 85 oC
Output enable pins for all
3.3 V power supply
buffered clocks
48-pin QFN package
Applications
Network attached storage
Multi-function printers
Wireless access point
Servers
Description
The Si53159 is a high-performance, low additive jitter, PCIe clock buffer
that can fan out nine PCIe clocks. The clock outputs are compliant to
PCIe Gen 1, Gen 2, Gen 3, and Gen 4 specifications. The device has six
hardware output enable control pins for enabling and disabling differential
outputs. The small footprint and low power consumption makes the
Si53159 the ideal clock solution for consumer and embedded
applications. Measuring PCIe clock jitter is quick and easy with the Silicon
Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-
learningcenter.
Functional Block Diagram
Ordering Information:
See page 18.
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37
VDD_DIFF 1
36 DIFF8
VDD_DIFF 2
35 DIFF8
OE_DIFF01 3
34 VDD_DIFF
OE_DIFF11 4
VDD_DIFF 5
VSS_DIFF 6
VSS_DIFF 7
OE_DIFF21 8
OE_DIFF31 9
OE_DIFF[4:5]1 10
OE_DIFF[6:8]1 11
VDD_DIFF 12
49
GND
33 DIFF7
32 DIFF7
31 DIFF6
30 DIFF6
29 VSS_DIFF
28 DIFF5
27 DIFF5
26 DIFF4
25 DIFF4
13 14 15 16 17 18 19 20 21 22 23 24
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
DIFFIN
DIFFIN
SCLK
SDATA
OE [8:0]
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
DIFF6
DIFF7
DIFF8
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53159




 SI53159
Si53159
2 Rev. 1.1




 SI53159
TABLE OF CONTENTS
Si53159
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. CKPWRGD/PDB (Power Down) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. PDB (Power Down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.4. OE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.5. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.6. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.1
3



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